公开(公告)号：US20060046367A1

公开(公告)日：2006-03-02

申请号：US10931195

申请日：2004-08-31

申请人： Antonio Rotondaro ,  Seetharaman Sridhar

发明人： Antonio Rotondaro ,  Seetharaman Sridhar

IPC分类号： H01L21/8238

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to channel regions of devices while mitigating masking operations employed. A CAPOLY layer is formed over an NMOS region of a semiconductor device (102). A recess etch is performed on active regions of devices within a PMOS region of the semiconductor device (104) and the CAPOLY layer prevents etching of devices within an NMOS region of the semiconductor device. Subsequently, an epitaxial formation process (106) is performed that forms or deposits epitaxial regions and introduces a first type of strain across the channel regions in the PMOS region. Then, the semiconductor device is annealed (108) to cause the CAPOLY layer to introduce a second type of strain across the channel regions in the NMOS region. After annealing, the CAPOLY layer is removed (110).

摘要翻译： 本发明通过提供制造方法来促进半导体制造，该方法选择性地将应变应用于器件的沟道区，同时减轻所采用的掩模操作。 在半导体器件（102）的NMOS区域上形成CAPOLY层。 在半导体器件（104）的PMOS区域内的器件的有源区域上执行凹蚀刻，并且CAPOLY层防止在半导体器件的NMOS区域内的器件的蚀刻。 随后，执行形成或沉积外延区域并在PMOS区域中的沟道区域上引入第一类型的应变的外延形成工艺（106）。 然后，半导体器件被退火（108）以使CAPOLY层在NMOS区域中的沟道区域上引入第二类型的应变。 退火后，去除CAPOLY层（110）。

公开(公告)号：US20050087810A1

公开(公告)日：2005-04-28

申请号：US10694237

申请日：2003-10-27

申请人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

发明人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8239 ,  H01L27/02 ,  H01L27/105 ,  H01L21/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L21/823807 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052

摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。

公开(公告)号：US06303420B1

公开(公告)日：2001-10-16

申请号：US09618413

申请日：2000-07-18

申请人： Seetharaman Sridhar ,  Amitava Chatterjee ,  Hisashi Shichijo ,  Alec J. Morton

发明人： Seetharaman Sridhar ,  Amitava Chatterjee ,  Hisashi Shichijo ,  Alec J. Morton

IPC分类号： H01L218238

CPC分类号： H01L21/8249

摘要： A method for forming integrated circuit bipolar junction transistors for mixed signal circuits. The implants used to form the well regions of the CMOS circuits 20, 40 form the collector regions of bipolar junction transistors. The CMOS transistor pocket implants form the base region of the bipolar junction transistor, and the CMOS drain extension implants form the emitter region of the bipolar junction transistor.

摘要翻译： 一种用于形成用于混合信号电路的集成电路双极结型晶体管的方法。 用于形成CMOS电路20,40的阱区域的种植体形成双极结型晶体管的集电极区域。 CMOS晶体管插入口形成双极结型晶体管的基极区域，并且CMOS漏极延伸注入形成双极结型晶体管的发射极区域。

公开(公告)号：US08114744B2

公开(公告)日：2012-02-14

申请号：US12345142

申请日：2008-12-29

申请人： Amitava Chatterjee ,  Seetharaman Sridhar ,  Xiaoju Wu ,  Vladimir F. Drobny

发明人： Amitava Chatterjee ,  Seetharaman Sridhar ,  Xiaoju Wu ,  Vladimir F. Drobny

IPC分类号： H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/76224 ,  H01L21/823878

摘要： A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges to the silicon including surface, and fabrication is then completed.

摘要翻译： 制造包括多个MOS晶体管和IC的集成电路（IC）的方法包括提供具有硅包含表面的衬底，以及在衬底中形成多个电介质填充的沟槽隔离区域，其中包含硅的表面形成沟槽 隔离有源区边缘沿其周边与沟槽隔离区。 沉积第一含硅层，其中第一硅包括从沟槽隔离有源区边缘上的沟槽隔离区的表面延伸到包含硅的表面。 第一硅包层被完全氧化以将第一硅层转化为氧化硅层，其中氧化硅层为多个MOS晶体管中的至少一个提供至少一部分栅极电介质。 在栅极电介质上形成图案化的栅极电极层，其中图案化的栅极电极层在至少一个沟槽隔离有源区边缘延伸到包含硅的表面，然后完成制造。

公开(公告)号：US08067279B2

公开(公告)日：2011-11-29

申请号：US12489223

申请日：2009-06-22

申请人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

发明人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

IPC分类号： H01L21/00

CPC分类号： H01L21/823807 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052

摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。

公开(公告)号：US08017493B2

公开(公告)日：2011-09-13

申请号：US12436973

申请日：2009-05-07

申请人： Abbas Ali ,  Seetharaman Sridhar

发明人： Abbas Ali ,  Seetharaman Sridhar

IPC分类号： H01L21/8238

CPC分类号： H01L21/76224

摘要： A process of forming a semiconductor process fabricated device which contains a trench, hole or gap filled with a conformally deposited material is disclosed. A sacrificial planarizing layer is formed on the fill material, and the device is planarized using a selective RIE process which etches the fill material faster than the sacrificial planarizing layer. An overetch step completes the planarization process.

摘要翻译： 公开了一种形成半导体工艺制造器件的方法，该器件包含填充有共形沉积材料的沟槽，孔或间隙。 在填充材料上形成牺牲平坦化层，并且使用选择性RIE工艺来平坦化器件，该选择性RIE工艺比牺牲平坦化层更快地蚀刻填充材料。 缓冲步骤完成平面化处理。

公开(公告)号：US20110076822A1

公开(公告)日：2011-03-31

申请号：US12961885

申请日：2010-12-07

申请人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

发明人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC分类号： H01L21/336

CPC分类号： H01L29/402 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device 100 comprising source and drain regions 105, 107, and insulating region 115 and a plate structure 140. The source and drain regions are on or in a semiconductor substrate 110. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer 120 and a thick layer 122. The thick layer includes a plurality of insulating stripes 132 that are separated from each other and that extend across a length 135 between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands 143 that are directly over individual ones of the plurality of insulating stripes.

摘要翻译： 包括源极和漏极区域105,107以及绝缘区域115和板状结构140的半导体器件100.源极和漏极区域在半导体衬底110上或半导体衬底110中。绝缘区域在半导体衬底上或半导体衬底中并且位于 源极和漏极区域。 绝缘区域具有薄层120和厚层122.厚层包括彼此分离并且跨越源极和漏极区域之间的长度135延伸的多个绝缘条132。 板结构位于源极和漏极区之间，其中板结构位于薄层上，厚层的部分，板结构具有一个或多个导电带143，其直接位于多个 绝缘条纹

公开(公告)号：US20090280618A1

公开(公告)日：2009-11-12

申请号：US12436973

申请日：2009-05-07

申请人： Abbas Ali ,  Seetharaman Sridhar

发明人： Abbas Ali ,  Seetharaman Sridhar

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： A process of forming a semiconductor process fabricated device which contains a trench, hole or gap filled with a conformally deposited material is disclosed. A sacrificial planarizing layer is formed on the fill material, and the device is planarized using a selective RIE process which etches the fill material faster than the sacrificial planarizing layer. An overetch step completes the planarization process.

摘要翻译： 公开了一种形成半导体工艺制造器件的方法，该器件包含填充有共形沉积材料的沟槽，孔或间隙。 在填充材料上形成牺牲平坦化层，并且使用选择性RIE工艺来平坦化器件，该选择性RIE工艺比牺牲平坦化层更快地蚀刻填充材料。 缓冲步骤完成平面化处理。

公开(公告)号：US20080283935A1

公开(公告)日：2008-11-20

申请号：US11750713

申请日：2007-05-18

申请人： Seetharaman Sridhar ,  Craig Hall

发明人： Seetharaman Sridhar ,  Craig Hall

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L29/06 ,  H01L29/94

CPC分类号： H01L21/823878 ,  H01L21/76232

摘要： The disclosure provides a trench isolation structure, a semiconductor device, and a method for manufacturing a semiconductor device. The semiconductor device, in one embodiment, includes a substrate having a first device region and a second device region, wherein the first device region includes a first gate structure and first source/drain regions and the second device region includes a second gate structure and second source/drain regions. The semiconductor device further includes a trench isolation structure configured to isolate the first device region from the second device region, the trench isolation structure comprising: 1) an isolation trench located within the substrate, wherein the isolation trench includes an opening portion and a bulbous portion, and further wherein a maximum width of the opening portion is less than a maximum width of the bulbous portion, and 2) dielectric material substantially filling the isolation trench.

摘要翻译： 本公开提供了沟槽隔离结构，半导体器件以及半导体器件的制造方法。 在一个实施例中，半导体器件包括具有第一器件区域和第二器件区域的衬底，其中第一器件区域包括第一栅极结构和第一源极/漏极区域，并且第二器件区域包括第二栅极结构和第二栅极结构 源/漏区。 所述半导体器件还包括被配置为将所述第一器件区域与所述第二器件区域隔离的沟槽隔离结构，所述沟槽隔离结构包括：1）位于所述衬底内的隔离沟槽，其中所述隔离沟槽包括开口部分和球形部分 并且其中所述开口部分的最大宽度小于所述球形部分的最大宽度，以及2）绝缘材料基本上填充所述隔离沟槽。

公开(公告)号：US20070020839A1

公开(公告)日：2007-01-25

申请号：US11184337

申请日：2005-07-19

申请人： Seetharaman Sridhar ,  Craig Hall ,  Che-Jen Hu ,  Antonio Luis Rotondaro

发明人： Seetharaman Sridhar ,  Craig Hall ,  Che-Jen Hu ,  Antonio Luis Rotondaro

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner is formed on the gate electrode layer. A resist mask is formed that defines gate structures. The gate electrode layer is patterned to form the gate structures. Offset spacers are formed on lateral edges of the gate structures and extension regions are then formed in the well regions. Sidewall spacers are then formed on the lateral edges of the gate structures. An NMOS protective region layer is formed that covers the NMOS region of the device. A recess etch is performed within the PMOS region followed by formation of strain inducing recess structures.

摘要翻译： 制造具有保护衬垫和/或层的半导体器件。 阱区和隔离区形成在半导体本体内。 栅电介质层形成在半导体本体上。 在栅极电介质层上形成诸如多晶硅的栅电极层。 在栅电极层上形成保护栅衬。 形成限定栅极结构的抗蚀剂掩模。 图案化栅极电极层以形成栅极结构。 偏移间隔件形成在栅极结构的横向边缘上，然后在阱区域中形成延伸区域。 然后在门结构的侧边缘上形成侧壁间隔物。 形成覆盖器件的NMOS区域的NMOS保护区域层。 在PMOS区域内执行凹陷蚀刻，随后形成应变引发凹陷结构。