公开(公告)号：US20240038529A1

公开(公告)日：2024-02-01

申请号：US18020288

申请日：2021-08-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yuji EGI ,  Yasuhiro JINBO ,  Hitoshi KUNITAKE

IPC: H01L21/02

CPC classification number: H01L21/0228 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02205 ,  H01L21/0234

Abstract: A method for depositing a metal oxide is provided. The deposition method of a metal oxide includes a first step of introducing a first precursor into a first chamber, a second step of introducing a second precursor into the first chamber, a third step of introducing a third precursor into the first chamber, a fourth step of introducing an oxidizer in a plasma state into the first chamber after each of the first step, the second step, and the third step, and a fifth step of performing microwave treatment. Performing each of the first to fourth steps one or more times is regarded as one cycle, and the fifth step is performed in a second chamber after the one cycle is repeated a plurality of times. The first to third precursors are different kinds of precursors, the microwave treatment is performed using an oxygen gas and an argon gas, the metal oxide includes a crystal region, and a c-axis of the crystal region is substantially parallel to a normal vector of a surface where the metal oxide is formed or a normal vector of a surface of the metal oxide.

公开(公告)号：US20230397427A1

公开(公告)日：2023-12-07

申请号：US18024285

申请日：2021-09-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Hitoshi KUNITAKE ,  Yuji EGI ,  Fumito ISAKA

IPC: H10B51/30 ,  H10B51/40 ,  H10B53/30 ,  H10B53/40 ,  H01L29/78 ,  H10B63/10 ,  H10N50/10

CPC classification number: H10B51/30 ,  H10B51/40 ,  H10B53/30 ,  H10B53/40 ,  H01L29/78391 ,  H10B63/10 ,  H10N50/10

Abstract: A semiconductor device that has lower power consumption and is capable of non-destructive reading is provided. The semiconductor device includes a first transistor, a first FTJ element, and a second FTJ element. A first terminal of the first transistor is electrically connected to an output terminal of the first FTJ element and an input terminal of the second FTJ element. In data writing, polarization is caused in each of the first FTJ element and the second FTJ element in accordance with the data. In data reading, voltage with which the polarization does not change is applied between the output terminal of the first FTJ element and the input terminal of the second FTJ element. At this time, the first transistor is turned on, whereby a differential current between current flowing through the first FTJ element and current flowing through the second FTJ element flows through the first transistor. Obtaining the differential current using a read circuit or the like enables the data written to the first FTJ element and the second FTJ element to be read.

公开(公告)号：US20230352090A1

公开(公告)日：2023-11-02

申请号：US17791326

申请日：2020-12-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuki TSUDA ,  Hiromichi GODO ,  Satoru OHSHITA ,  Hitoshi KUNITAKE ,  Satoru OKAMOTO

IPC: G11C16/04 ,  H01L29/786 ,  H01L23/528 ,  H10B43/10 ,  H10B43/35 ,  H10B43/27

CPC classification number: G11C16/0483 ,  H01L29/7869 ,  H01L23/5283 ,  H10B43/10 ,  H10B43/35 ,  H10B43/27

Abstract: A highly reliable memory device is provided. The memory device includes a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and a second semiconductor. At least third conductor and the fourth conductor have an opening. The first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order on an inner surface of the opening. The seventh conductor is provided between the first semiconductor and the second insulator in a region between the third conductor and the second insulator. The first semiconductor is electrically connected to the second conductor and the fifth conductor. The second semiconductor is electrically connected to the first conductor and the sixth conductor.

公开(公告)号：US20230269949A1

公开(公告)日：2023-08-24

申请号：US18043669

申请日：2021-08-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Yasuhiro JINBO ,  Hitoshi KUNITAKE ,  Yuji EGI ,  Masahiro TAKAHASHI ,  Shuntaro KOCHI

IPC: H10B53/30 ,  H10B53/10 ,  H01L29/786 ,  H01L29/66

CPC classification number: H10B53/30 ,  H10B53/10 ,  H01L29/78696 ,  H01L29/7869 ,  H01L29/6675

Abstract: A material having favorable ferroelectricity is provided. An embodiment of the present invention is a metal oxide film including a first layer and a second layer. The first layer contains first oxygen and hafnium, and the second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other with the first oxygen positioned therebetween, and the second oxygen is bonded to the zirconium.

公开(公告)号：US20220399370A1

公开(公告)日：2022-12-15

申请号：US17776388

申请日：2020-11-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiromi SAWAI ,  Tsutomu MURAKAWA ,  Hitoshi KUNITAKE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/535

Abstract: A highly reliable memory device is provided. In a method for manufacturing a memory device that includes a first insulator, a first conductor including a first opening over the first insulator, a second insulator including a second opening over the first conductor, a second conductor including a third opening over the second insulator, a third insulator over the second conductor, and a semiconductor provided in the first opening to the third opening, the first insulator is formed, the first conductor is formed over the first insulator, the second insulator is formed over the first conductor, a fourth insulator is formed over the second insulator, the third insulator is formed over the fourth insulator, the third opening is formed in the fourth insulator, the second opening is formed in the second insulator, the first opening is formed in the first conductor, the semiconductor is formed in the first opening to the third opening, the fourth insulator is removed, and the second conductor is formed between the second insulator and the third insulator.

公开(公告)号：US20220375956A1

公开(公告)日：2022-11-24

申请号：US17772280

申请日：2020-11-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Satoru OHSHITA ,  Kazuki TSUDA ,  Tatsuya ONUKI

IPC: H01L27/11573 ,  H01L27/11582 ,  G11C16/08

Abstract: A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.

公开(公告)号：US20220375529A1

公开(公告)日：2022-11-24

申请号：US17772740

申请日：2020-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takayuki IKEDA ,  Hitoshi KUNITAKE

IPC: G11C16/26

Abstract: A low-power memory device in which a NAND flash memory and a controller are connected to each other with a short wiring, the controller and a cache memory are connected to each other with a short wiring, and signal transmission delay is small is provided. For example, the NAND flash memory is formed using a Si transistor formed with a single crystal silicon substrate. Since an OS transistor can be formed by a method such as a thin-film method, the cache memory formed using the OS memory can be stacked over the NAND flash memory. When the NAND flash memory and the cache memory are formed in one chip, the NAND flash memory and the controller can be connected to each other with a short wiring, and the controller and the cache memory can be connected to each other with a short wiring.

公开(公告)号：US20220375521A1

公开(公告)日：2022-11-24

申请号：US17773887

申请日：2020-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takayuki IKEDA ,  Hitoshi KUNITAKE

IPC: G11C14/00 ,  H01L27/11582

Abstract: A computer system with a small circuit area and reduced power consumption is used. The computer system includes a computer node including a processor and a three-dimensional NAND memory device. The three-dimensional NAND memory device includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell. Thus, the computer node can eliminate a main memory such as a DRAM from the structure.

公开(公告)号：US20220345095A1

公开(公告)日：2022-10-27

申请号：US17619669

申请日：2020-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Takayuki IKEDA ,  Kiyoshi KATO ,  Yuichi YANAGISAWA ,  Shota MIZUKAMI ,  Kazuki TSUDA

IPC: H03F3/195 ,  H03F1/02 ,  H01L29/786

Abstract: A semiconductor device is provided in which power consumption is reduced and an increase in circuit area is inhibited. The semiconductor device includes a high frequency amplifier circuit, an envelope detection circuit, and a power supply circuit. The power supply circuit has a function of supplying a power supply potential to the high frequency amplifier circuit, an output of the high frequency amplifier circuit is connected to the envelope detection circuit, and an output of the envelope detection circuit is connected to the power supply circuit. The power supply circuit can reduce the power consumption by changing the power supply potential in accordance with the output of the high frequency amplifier circuit. The use of an OS transistor in the envelope detection circuit can inhibit an increase in circuit area.

公开(公告)号：US20220328516A1

公开(公告)日：2022-10-13

申请号：US17640549

申请日：2020-09-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Hitoshi KUNITAKE

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device with high storage capacity is provided. The semiconductor device includes first to sixth insulators, first to third conductors, and first to third material layers. The first conductor overlaps with a first insulator and a first material layer. A first region of the first material layer overlaps with a second material layer, a second conductor, a second insulator, and a third insulator. The third material layer is positioned in a region including a second region of the first material layer and top surfaces of the second material layer, the second conductor, the second insulator, and the third insulator; a fourth insulator is positioned over the third material layer; the sixth insulator is positioned over the fourth insulator; and a fifth insulator is positioned over the sixth insulator. The third conductor is positioned over the fifth insulator overlapping with the second region of the first material layer. The first to third material layers include oxide containing indium, an element M (M is aluminum, gallium, tin, or titanium), and zinc.