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    Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes
    22.
    发明授权
    Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes 有权
    用于形成使用多个独立形成的封盖材料层以减少针孔的硬掩模的方法

    公开(公告)号：US07183198B2

    公开(公告)日：2007-02-27

    申请号：US10962907

    申请日：2004-10-12

    申请人： Pei-Yuan Gao ,  Lu You ,  Richard J. Huang

    发明人： Pei-Yuan Gao ,  Lu You ,  Richard J. Huang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/0332 ,  H01L21/32139 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.

    摘要翻译： 双层BARC /硬掩模结构包括非晶碳层和形成在无定形碳层上的诸如SiON的PECVD材料的两个或更多个不同且独立形成的层。 通过独立地形成多层PECVD材料，存在于最低PECVD层中的至少一些针孔由上PECVD层封闭，因此不延伸穿过所有PECVD层。 结果，最上面的PECVD层的上表面具有比下PECVD层更低的针孔密度。 这减少了无定形碳层中的掺杂剂的光致抗蚀剂中毒，以及通过光刻胶剥离化学法蚀刻无定形碳层。

    Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices
    23.
    发明授权
    Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices 有权
    单独使用BPTEOS ILD或BPTEOS ILD的薄的未掺杂TEOS来改善多位存储器件中的电荷损耗和接触电阻

    公开(公告)号：US07157335B1

    公开(公告)日：2007-01-02

    申请号：US10917562

    申请日：2004-08-13

    申请人： Ning Cheng ,  Minh Van Ngo ,  Hirokazu Tokuno ,  Lu You ,  Angela T. Hui ,  Yi He ,  Brian Mooney ,  Jean Yei-Mei Yang ,  Mark T. Ramsbey

    发明人： Ning Cheng ,  Minh Van Ngo ,  Hirokazu Tokuno ,  Lu You ,  Angela T. Hui ,  Yi He ,  Brian Mooney ,  Jean Yei-Mei Yang ,  Mark T. Ramsbey

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.

    摘要翻译： 本发明通过提供在制造期间使用相对薄的未掺杂TEOS衬垫的系统和方法而不是通常使用的相对较厚的TEOS层来便于双位存储器件和双位存储器件的操作。 使用相对薄的衬垫通过减轻电荷损失和接触电阻而提供双位存储器件操作，同时提供防止不期望的掺杂剂扩散的保护。 本发明包括利用形成在字线和电荷捕获电介质层的部分上的相对薄的未掺杂的TEOS衬垫。 相对薄的未掺杂的TEOS衬垫形成有小于约400埃的厚度，使得接触电阻和电荷损失得到改善，并且为器件的操作提供适当的保护。 此外，本发明包括前述的未掺杂的TEOS衬垫。

    Multi-chamber deposition of silicon oxynitride film for patterning
    24.
    发明授权
    Multi-chamber deposition of silicon oxynitride film for patterning 失效
    用于图案化的氮氧化硅膜的多室沉积

    公开(公告)号：US07033960B1

    公开(公告)日：2006-04-25

    申请号：US10918378

    申请日：2004-08-16

    申请人： Lu You ,  Richard Huang ,  Pei-Yuan Gao

    发明人： Lu You ,  Richard Huang ,  Pei-Yuan Gao

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/32139 ,  C23C16/345 ,  H01L21/0332 ,  H01L21/3145 ,  H01L21/3146 ,  Y10S438/95

    摘要： Pinholes in a silicon oxynitride film are reduced by PECVD deposition of a plurality of silicon oxynitride sub-layers in a PECVD apparatus containing multiple chambers. Embodiments include forming a layer of amorphous carbon over a conductive layer, such as doped polycrystalline silicon, on a substrate, transferring the substrate to a multi-chamber PECVD tool and depositing 2 to 7, e.g., 5, sub-layers of dense silicon oxynitride at a total thickness of 300 to 700 Å.

    摘要翻译： 氧氮化硅膜中的针孔通过在包含多个室的PECVD装置中的多个氮氧化硅子层的PECVD沉积而减少。 实施例包括在衬底上的导电层（例如掺杂多晶硅）上形成无定形碳层，将衬底转移到多室PECVD工具，并沉积2至7个例如5个致密氮氧化硅的子层 总厚度为300至700埃。

    Dual damascene integration scheme for preventing copper contamination of dielectric layer
    25.
    发明授权
    Dual damascene integration scheme for preventing copper contamination of dielectric layer 有权
    用于防止介电层铜污染的双镶嵌一体化方案

    公开(公告)号：US06939793B1

    公开(公告)日：2005-09-06

    申请号：US10422784

    申请日：2003-04-25

    申请人： Lu You ,  Fei Wang ,  Christy Woo

    发明人： Lu You ,  Fei Wang ,  Christy Woo

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

    CPC分类号： H01L21/76831 ,  H01L21/76804 ,  H01L21/76813 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.

    摘要翻译： 半导体器件包括第一金属化层，第一扩散阻挡层，第二蚀刻停止层，第一介电层，第一蚀刻停止层，第二介电层，延伸穿过第二介电层的沟槽和第一蚀刻停止层 层，以及延伸穿过第一介电层，第二蚀刻停止层和第一扩散阻挡层的通孔。 第一扩散阻挡层设置在第一金属化层上。 第二蚀刻停止层设置在第一扩散阻挡层之上并与第一扩散阻挡层隔开，并且第一介电层设置在第二蚀刻停止层上。 通孔也可以有圆角。 第三蚀刻停止层也可以设置在第一扩散阻挡层和第二蚀刻停止层之间。 侧壁扩散阻挡层可以设置在通孔和沟槽的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 还公开了制造半导体器件的方法。

    Hardmask employing multiple layers of silicon oxynitride
    27.
    发明申请
    Hardmask employing multiple layers of silicon oxynitride 有权
    使用多层氮氧化硅的硬掩模

    公开(公告)号：US20050048771A1

    公开(公告)日：2005-03-03

    申请号：US10962907

    申请日：2004-10-12

    申请人： Pei-Yuan Gao ,  Lu You ,  Richard Huang

    发明人： Pei-Yuan Gao ,  Lu You ,  Richard Huang

    IPC分类号： H01L21/033 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/0332 ,  H01L21/32139 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.

    摘要翻译： 双层BARC /硬掩模结构包括非晶碳层和形成在无定形碳层上的诸如SiON的PECVD材料的两个或更多个不同且独立形成的层。 通过独立地形成多层PECVD材料，存在于最低PECVD层中的至少一些针孔由上PECVD层封闭，因此不延伸穿过所有PECVD层。 结果，最上面的PECVD层的上表面具有比下PECVD层更低的针孔密度。 这减少了无定形碳层中的掺杂剂的光致抗蚀剂中毒，以及通过光刻胶剥离化学法蚀刻无定形碳层。

    Use of sic for preventing copper contamination of low-k dielectric layers
    28.
    发明授权
    Use of sic for preventing copper contamination of low-k dielectric layers 有权
    使用sic来防止低k电介质层的铜污染

    公开(公告)号：US06756672B1

    公开(公告)日：2004-06-29

    申请号：US09776750

    申请日：2001-02-06

    申请人： Lu You ,  Dawn M. Hopper ,  Suzette K. Pangrle

    发明人： Lu You ,  Dawn M. Hopper ,  Suzette K. Pangrle

    IPC分类号： H01L2348

    CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76813 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from silicon carbide. A method of manufacturing the semiconductor device is also disclosed.

    摘要翻译： 半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。 第一扩散阻挡层设置在第一金属化层上。 第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。 通孔也可以有圆角。 侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 第一蚀刻停止层可以由碳化硅形成。 还公开了制造半导体器件的方法。

    Method for forming dual damascene interconnect structure
    29.
    发明授权
    Method for forming dual damascene interconnect structure 有权
    双镶嵌互连结构的形成方法

    公开(公告)号：US06756300B1

    公开(公告)日：2004-06-29

    申请号：US10324259

    申请日：2002-12-18

    申请人： Fei Wang ,  Jerry Cheng ,  Lynne A. Okada ,  Minh Quoc Tran ,  Lu You

    发明人： Fei Wang ,  Jerry Cheng ,  Lynne A. Okada ,  Minh Quoc Tran ,  Lu You

    IPC分类号： H01L214763

    CPC分类号： H01L21/76811 ,  H01L21/76813

    摘要： For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.

    摘要翻译： 为了在介电材料内形成双镶嵌开口，在电介质材料上形成通孔掩模材料和沟槽掩模材料。 通过沟槽掩模材料形成沟槽开口，并且通过布置在通孔和沟槽掩模材料上方的通孔掩模图案形成材料形成通孔开口。 通过通孔掩模图形材料的通路孔露出的通孔和沟槽掩模材料被蚀刻掉，并且通孔掩模图案材料被蚀刻掉。 通过通孔开口暴露的介电材料的一部分被蚀刻到下面的互连结构上，并且蚀刻通过沟槽开口露出的电介质材料的一部分，以形成双镶嵌开口。