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    Multi-Layer Electrode Structure
    22.
    发明申请
    Multi-Layer Electrode Structure 有权
    多层电极结构

    公开(公告)号：US20080142984A1

    公开(公告)日：2008-06-19

    申请号：US11611428

    申请日：2006-12-15

    Applicant: Shih-Hung Chen

    Inventor： Shih-Hung Chen

    IPC: H01L23/48 ,  H01L21/44

    CPC classification number: H01L45/144 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

    Abstract: An electrode structure including two parallel electrical paths. A plurality of electrode layers, generally tabular in form is formed in a stack, the outermost layers providing electrical contacts, and defining a first electrical current path through the stack. Two sidewall conductor layers are formed to abut either end of the electrode layer stack, two sidewall conductor layers defining a second electrical current path. The ends of the sidewall conduction layers lie in the same planes as the electrode layer electrical contacts, such that electrode structure electrical contacts are each formed from one set of sidewall layer ends and an electrode layer electrical contact.

    Abstract translation: 一种包括两个平行电路的电极结构。 多个电极层通常以叠片的形式形成在堆叠中，最外层提供电触点，并且限定穿过叠层的第一电流路径。 形成两个侧壁导体层以邻接电极层堆叠的任一端，限定第二电流路径的两个侧壁导体层。 侧壁导电层的端部位于与电极层电接触相同的平面中，使得电极结构电触头各自由一组侧壁层端部和电极层电接触形成。

    Self-Aligned Structure and Method for Confining a Melting Point in a Resistor Random Access Memory
    23.
    发明申请
    Self-Aligned Structure and Method for Confining a Melting Point in a Resistor Random Access Memory 有权
    用于限制电阻随机存取存储器中的熔点的自对准结构和方法

    公开(公告)号：US20080121861A1

    公开(公告)日：2008-05-29

    申请号：US11465094

    申请日：2006-08-16

    Applicant: Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

    Inventor： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

    Abstract: A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

    Abstract translation: 制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。 该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料， 选择性材料。 柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。 可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

    ESD PROTECTION CIRCUIT USING SELF-BIASED CURRENT TRIGGER TECHNIQUE AND PUMPING SOURCE MECHANISM
    24.
    发明申请
    ESD PROTECTION CIRCUIT USING SELF-BIASED CURRENT TRIGGER TECHNIQUE AND PUMPING SOURCE MECHANISM 有权
    使用自偏移电流触发技术和泵浦源机制的ESD保护电路

    公开(公告)号：US20080062598A1

    公开(公告)日：2008-03-13

    申请号：US11740904

    申请日：2007-04-26

    Applicant: Shih-Hung Chen ,  Ming-Dou Ker

    Inventor： Shih-Hung Chen ,  Ming-Dou Ker

    IPC: H02H9/04

    CPC classification number: H01L27/0266

    Abstract: A circuit capable of providing electrostatic discharge (ESD) protection includes a first transistor including a first gate and a first source, the first gate being connected to a conductive pad, an impedance device between the first source and a first power rail capable of providing a resistor, a second transistor including a second gate and a second source, the second source being connected to the first power rail through the impedance device, and a clamp device between the first power rail and a second power rail, wherein the clamp device is capable of conducting a first portion of an ESD current and the second transistor is capable of conducting a second portion of the ESD current as the conductive pad is relatively grounded.

    Abstract translation: 能够提供静电放电（ESD）保护的电路包括：第一晶体管，包括第一栅极和第一源极，第一栅极连接到导电焊盘，第一源极与能够提供 电阻器，包括第二栅极和第二源极的第二晶体管，所述第二源极通过所述阻抗器件连接到所述第一电力轨道，以及在所述第一电力轨道和第二电力轨道之间的夹紧装置，其中所述夹紧装置能够 导电ESD电流的第一部分，并且当导电焊盘相对接地时，第二晶体管能够导通ESD电流的第二部分。

    Non-volatile memory cell and operating method thereof
    25.
    发明申请
    Non-volatile memory cell and operating method thereof 审中-公开
    非易失性存储单元及其操作方法

    公开(公告)号：US20060126395A1

    公开(公告)日：2006-06-15

    申请号：US11180093

    申请日：2005-07-11

    Applicant: Shih-Hung Chen ,  Yi-Chou Chen

    Inventor： Shih-Hung Chen ,  Yi-Chou Chen

    IPC: G11C16/04 ,  G11C11/34

    CPC classification number: G11C13/0004 ,  G11C13/003 ,  G11C2213/76

    Abstract: A non-volatile memory cell is provided. The non-volatile memory cell includes of a threshold switch material thin film and a memory switch material thin film, and the phases of the memory switch material layer is capable of changing. In addition, the memory switch material layer serves as a memory unit; the threshold switch material serves as a steering unit. Furthermore, the steering unit will breakdown when a voltage larger than its threshold voltage is provided, and the phase restores to the original state when the voltage is off.

    Abstract translation: 提供非易失性存储单元。 非易失性存储单元包括阈值开关材料薄膜和存储器开关材料薄膜，并且存储器开关材料层的相位能够改变。 此外，存储器开关材料层用作存储器单元; 阈值开关材料用作转向单元。 此外，当提供大于其阈值电压的电压时，转向单元将击穿，并且当电压关闭时，相位恢复到原始状态。

    Integrated circuit capacitor and method
    26.
    发明授权
    Integrated circuit capacitor and method 有权
    集成电路电容及方法

    公开(公告)号：US09048341B2

    公开(公告)日：2015-06-02

    申请号：US13451428

    申请日：2012-04-19

    Applicant: Shih-Hung Chen ,  Kuang-Yeu Hsieh

    Inventor： Shih-Hung Chen ,  Kuang-Yeu Hsieh

    IPC: H01L21/02 ,  H01L49/02

    CPC classification number: H01L28/91

    Abstract: An example of a capacitor includes a series of ridges and trenches and an interconnect region on the integrated circuit substrate. The series of ridges and trenches and the interconnect region have a capacitor foundation surface with a serpentine cross-sectional shape on the series of ridges and trenches. Electrical conductors are electrically connected to the electrode layers from the interconnect region for access to the electrode layers of the capacitor assembly.

    Abstract translation: 电容器的示例包括集成电路基板上的一系列脊和沟槽和互连区域。 一系列脊和沟槽和互连区域具有在一系列脊和沟槽上具有蛇形横截面形状的电容器基座表面。 电导体从互连区域电连接到电极层，用于进入电容器组件的电极层。

    Three dimensional memory array adjacent to trench sidewalls
    27.
    发明授权
    Three dimensional memory array adjacent to trench sidewalls 有权
    与沟槽侧壁相邻的三维存储器阵列

    公开(公告)号：US09035275B2

    公开(公告)日：2015-05-19

    申请号：US13330525

    申请日：2011-12-19

    Applicant: Wei-Chih Chien ,  Ming-Hsiu Lee ,  Shih-Hung Chen

    Inventor： Wei-Chih Chien ,  Ming-Hsiu Lee ,  Shih-Hung Chen

    IPC: H01L29/06 ,  H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633

    Abstract: A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.

    Abstract translation: 一种自对准堆叠式存储单元阵列结构及其制造方法。 存储单元阵列包括与形成在沟槽内的导电线的相对侧相邻设置的一堆存储单元。 存储单元被堆叠，使得每个存储单元的存储元件表面形成导电线的侧壁的一部分。 导电线形成在沟槽内，使得电接触跨越每个存储单元的整个存储元件表面。 用于制造这种结构的这种结构和方法是不需要使用任何附加掩模的自对准过程。

    Damascene word line
    28.
    发明授权
    Damascene word line 有权
    大马士革字线

    公开(公告)号：US08987098B2

    公开(公告)日：2015-03-24

    申请号：US13527259

    申请日：2012-06-19

    Applicant: Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

    Inventor： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

    IPC: H01L21/336 ,  H01L27/115

    CPC classification number: H01L27/11578 ,  H01L27/11565

    Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.

    Abstract translation: 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。 通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。 在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

    Loadport bridge for semiconductor fabrication tools
    29.
    发明授权
    Loadport bridge for semiconductor fabrication tools 有权
    用于半导体制造工具的承载桥

    公开(公告)号：US08944739B2

    公开(公告)日：2015-02-03

    申请号：US13486024

    申请日：2012-06-01

    Applicant: Shih-Hung Chen ,  Ying Xiao ,  Chin-Hsiang Lin

    Inventor： Shih-Hung Chen ,  Ying Xiao ,  Chin-Hsiang Lin

    IPC: H01L21/677

    CPC classification number: H01L21/6773 ,  H01L21/67733 ,  H01L21/67775

    Abstract: A wafer handling system with apparatus for transporting wafers between semiconductor fabrication tools. In one embodiment, the apparatus is a loadport bridge mechanism including an enclosure having first and second mounting ends, a docking port at each end configured and dimensioned to interface with a loadport of a semiconductor tool, and at least one wafer transport robot operable to transport a wafer between the docking ports. The wafer transport robot hands off or receives a wafer to/from a tool robot at the loadports of a first and second tool. The bridge mechanism allows one or more wafers to be transferred between loadports of different tools on an individual basis without reliance on the FAB's automated material handling system (AMHS) for bulk wafer transport inside a wafer carrier such as a FOUP or others.

    Abstract translation: 一种具有用于在半导体制造工具之间传输晶片的装置的晶片处理系统。 在一个实施例中，该装置是装载端口机构，其包括具有第一和第二安装端的外壳，每个端部处的对接端口被构造和尺寸设计成与半导体工具的承载端口相接合，以及至少一个可运输的晶片传送机械手 在对接端口之间的晶片。 晶片传送机器人在第一和第二工具的载荷端口移动或接收来自工具机器人的晶片。 桥接机构允许一个或多个晶片在不同工具的载荷端口之间单独传输，而不依赖于FAB的自动化材料处理系统（AMHS），用于在诸如FOUP或其它晶片载体之间的体晶片传输。

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