公开(公告)号：US08325516B2

公开(公告)日：2012-12-04

申请号：US12603779

申请日：2009-10-22

申请人： Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

发明人： Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

IPC分类号： G11C11/34

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/7881

摘要： A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.

摘要翻译： 分离门存储单元。 第一和第二导电类型的第一和第二阱区域形成在衬底中。 浮置栅极设置在第一阱区和第二阱区的接合处并且与衬底绝缘。 控制栅极设置在浮动栅极的侧壁上并与基板和浮动栅极绝缘，并且部分地延伸到浮动栅极的上表面。 在第二阱区中形成第一导电类型的掺杂区域。 第一阱区域和掺杂区域分别用作分裂栅极存储单元的源极和漏极区域。

公开(公告)号：US08183910B2

公开(公告)日：2012-05-22

申请号：US12495024

申请日：2009-06-30

申请人： Shine Chung ,  Fu-Lung Hsueh

发明人： Shine Chung ,  Fu-Lung Hsueh

IPC分类号： H01L35/00 ,  H01L37/00 ,  H03K3/42 ,  H03K17/78

CPC分类号： G01R31/3004 ,  G01R31/31703

摘要： A circuit and method for a digital process monitor is disclosed. Circuits for comparing a current or voltage to a current or voltage corresponding to a device having process dependent circuit characteristics are disclosed, having converters for converting current or voltage measurements proportional to the process dependent circuit characteristic to a digital signal and outputting the digital signal for monitoring. The process dependent circuit characteristics may be selected from transistor threshold voltage, transistor saturation current, and temperature dependent quantities. Calibration is performed using digital techniques such as digital filtering and digital signal processing. The digital process monitor circuit may be formed as a scribe line circuit for wafer characterization or placed in an integrated circuit die as a macro. The process monitor circuit may be accessed using probe pads or scan test circuitry. Methods for monitoring process dependent characteristics using digital outputs are disclosed.

摘要翻译： 公开了一种用于数字处理监视器的电路和方法。 公开了用于将电流或电压与对应于具有过程相关电路特性的器件相对应的电流或电压进行比较的电路，具有用于将与过程相关的电路特性成比例的电流或电压测量值转换为数字信号的转换器，并输出用于监测的数字信号 。 处理相关电路特性可以选自晶体管阈值电压，晶体管饱和电流和温度依赖量。 使用数字滤波和数字信号处理等数字技术进行校准。 数字处理监视电路可以形成为用于晶片表征的划线电路或者作为宏放置在集成电路管芯中。 可以使用探针焊盘或扫描测试电路来访问过程监控电路。 公开了使用数字输出来监视与过程有关的特性的方法。

公开(公告)号：US07760144B2

公开(公告)日：2010-07-20

申请号：US12185591

申请日：2008-08-04

申请人： Chung-Long Chang ,  David Ding-Chung Lu ,  Shine Chung

发明人： Chung-Long Chang ,  David Ding-Chung Lu ,  Shine Chung

IPC分类号： H01Q1/38 ,  H01Q1/24

CPC分类号： H01Q23/00 ,  H01L23/585 ,  H01L23/66 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48195 ,  H01L2224/484 ,  H01L2225/06506 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01Q1/38 ,  H01L2224/45099 ,  H01L2924/00012

摘要： An integrated circuit structure includes a semiconductor chip including a top surface, a bottom surface, and a side surface; a metal seal ring adjacent the side surface; and an antenna including a seal-ring antenna. The seal-ring antenna includes at least a portion of the metal seal ring.

摘要翻译： 集成电路结构包括：半导体芯片，包括顶表面，底表面和侧表面; 靠近侧面的金属密封环; 以及包括密封环天线的天线。 所述密封环天线包括所述金属密封环的至少一部分。

公开(公告)号：US07663445B2

公开(公告)日：2010-02-16

申请号：US12237187

申请日：2008-09-24

申请人： Shine Chung ,  Fu-Lung Hsueh

发明人： Shine Chung ,  Fu-Lung Hsueh

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1203 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/124

摘要： A voltage controlled oscillator includes: a first merged device having a first bipolar transistor and a first MOS transistor, the first bipolar transistor having a collector sharing a common active area with a source/drain of the first MOS transistor, and an emitter sharing the common active area with another source/drain of the first MOS transistor, a second merged device having a second bipolar transistor and a second MOS transistor, the second bipolar transistor having a collector sharing a common active area with a source/drain of the second MOS transistor, and an emitter sharing the common active area with another source/drain of the second MOS transistor, and a first inductor connected to both the collector of the first bipolar transistor and a base of the second bipolar transistor.

摘要翻译： 压控振荡器包括：具有第一双极晶体管和第一MOS晶体管的第一合并器件，所述第一双极晶体管具有与第一MOS晶体管的源极/漏极共用公共有效面积的集电极，以及共享公共 具有第一MOS晶体管的另一源/漏极的有源区，具有第二双极晶体管和第二MOS晶体管的第二合并器件，所述第二双极晶体管具有与第二MOS晶体管的源极/漏极共用共用有效面积的集电极 以及与第二MOS晶体管的另一个源极/漏极共用公共有源区域的发射极，以及连接到第一双极晶体管的集电极和第二双极晶体管的基极的第一电感器。

公开(公告)号：US20100026601A1

公开(公告)日：2010-02-04

申请号：US12185591

申请日：2008-08-04

申请人： Chung-Long Chang ,  David Ding-Chung Lu ,  Shine Chung

发明人： Chung-Long Chang ,  David Ding-Chung Lu ,  Shine Chung

IPC分类号： H01Q19/10

CPC分类号： H01Q23/00 ,  H01L23/585 ,  H01L23/66 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48195 ,  H01L2224/484 ,  H01L2225/06506 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01Q1/38 ,  H01L2224/45099 ,  H01L2924/00012

摘要： An integrated circuit structure includes a semiconductor chip including a top surface, a bottom surface, and a side surface; a metal seal ring adjacent the side surface; and an antenna including a seal-ring antenna. The seal-ring antenna includes at least a portion of the metal seal ring.

摘要翻译： 集成电路结构包括：半导体芯片，包括顶表面，底表面和侧表面; 靠近侧面的金属密封环; 以及包括密封环天线的天线。 密封环天线包括金属密封环的至少一部分。

公开(公告)号：US20090296448A1

公开(公告)日：2009-12-03

申请号：US12367455

申请日：2009-02-06

申请人： Fu Lung Hsueh ,  Shine Chung ,  Wen-Kuan Fang

发明人： Fu Lung Hsueh ,  Shine Chung ,  Wen-Kuan Fang

IPC分类号： G11C17/06 ,  G11C5/14 ,  G11C17/00 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C5/00

摘要： A voltage down converter for programming a one-time-programmable (OTP) memory comprising is disclosed, the voltage down converter comprises a bonding pad for coupling to a programming power supply, and at least one forward biased diode coupled between the bonding pad and the OTP memory, wherein a programming voltage received by the OTP memory is lowered from the programming power supply by the voltage drop across the forward biased diode.

摘要翻译： 公开了一种用于对一次可编程（OTP）存储器进行编程的降压转换器，所述降压转换器包括用于耦合到编程电源的接合焊盘，以及耦合在所述接合焊盘和所述接合焊盘之间的至少一个正向偏置二极管 OTP存储器，其中由OTP存储器接收的编程电压通过正向偏置二极管上的电压降从编程电源降低。

公开(公告)号：US07626224B2

公开(公告)日：2009-12-01

申请号：US11531295

申请日：2006-09-13

申请人： Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

发明人： Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

IPC分类号： H01L29/788

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/7881

摘要： A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.

摘要翻译： 分离门存储单元。 第一和第二导电类型的第一和第二阱区域形成在衬底中。 浮置栅极设置在第一阱区和第二阱区的接合处并且与衬底绝缘。 控制栅极设置在浮动栅极的侧壁上并与基板和浮动栅极绝缘，并且部分延伸到浮动栅极的上表面。 在第二阱区中形成第一导电类型的掺杂区域。 第一阱区域和掺杂区域分别用作分裂栅极存储单元的源极和漏极区域。

公开(公告)号：US07612638B2

公开(公告)日：2009-11-03

申请号：US11486903

申请日：2006-07-14

申请人： Shine Chung ,  Fu-Lung Hsueh

发明人： Shine Chung ,  Fu-Lung Hsueh

IPC分类号： H01P3/00 ,  H01P3/12 ,  H01P3/14 ,  H01P1/00 ,  H01P1/06

CPC分类号： H01P3/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A waveguide in semiconductor integrated circuit is disclosed, the waveguide comprises a horizontal first metal plate, a horizontal second metal plate above the first metal plate, separated by an insulation material, and a plurality of metal vias positioned in two parallel lines, running vertically through the insulation material in contacts with both the first and second metal plates, wherein the first and second metal plates and the plurality of metal vias form a metal enclosure in a cross-sectional view that can serve as a waveguide.

摘要翻译： 公开了一种半导体集成电路中的波导，波导包括水平的第一金属板，在第一金属板上方的水平的第二金属板，由绝缘材料隔开，并且多个金属通孔位于两条平行的线上，垂直延伸穿过 所述绝缘材料与所述第一和第二金属板两者接触，其中所述第一和第二金属板和所述多个金属通孔以横截面视图形成可用作波导的金属外壳。

公开(公告)号：US20090002058A1

公开(公告)日：2009-01-01

申请号：US11769611

申请日：2007-06-27

申请人： Po Yao Ker ,  Shine Chung ,  Fu-Lung Hsueh

发明人： Po Yao Ker ,  Shine Chung ,  Fu-Lung Hsueh

IPC分类号： H01H37/76 ,  G11C5/14

CPC分类号： G11C17/18 ,  G11C5/147

摘要： The present invention discloses a bias circuit for a sense amplifier having a device under sensing, the device under sensing having an un-programmed state and a programmed state, the bias circuit comprises at least one first branch having at least one first device formed substantially the same as the device under sensing and remaining in the un-programmed state, and at least one second device formed also substantially the same as the device under sensing and being in the programmed state, wherein the at least one first device and the at least one second device are serially connected. A typical application of the present invention is an electrical fuse memory.

摘要翻译： 本发明公开了一种用于感测放大器的偏置电路，其具有被感测的器件，该感测器件处于非编程状态和编程状态，该偏置电路包括至少一个第一分支，该第一分支具有至少一个基本上形成 与感测下的设备相同并且保持在未编程状态，并且至少一个第二设备形成也与感测下的设备基本相同并处于编程状态，其中至少一个第一设备和至少一个 第二设备串联连接。 本发明的典型应用是电熔丝存储器。

公开(公告)号：US20080258255A1

公开(公告)日：2008-10-23

申请号：US11738868

申请日：2007-04-23

申请人： Po-Yao Ker ,  Shine Chung

发明人： Po-Yao Ker ,  Shine Chung

IPC分类号： H01L23/52 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure with aggravated electromigration effect is disclosed, which comprises an anode area overlaying a first plurality of contacts that are coupled to a positively high voltage during a programming of the fuse structure, a cathode area overlaying a second plurality of contacts that are coupled to a complementary low voltage during a programming of the fuse structure, and a fuse link area having a first and second end, wherein the first end contacts the anode area at a predetermined distance to the nearest of the first plurality of contacts, and the second end contacts the cathode area at the predetermined distance to the nearest of the second plurality of contacts, wherein the cathode area is smaller than the anode area for the aggravating electromigration effect.

摘要翻译： 公开了一种具有恶化的电迁移效应的熔丝结构，其包括在熔丝结构的编程期间覆盖耦合到正高电压的第一多个触点的阳极区域，覆盖第二多个触点的阴极区域， 在熔丝结构的编程期间的互补的低电压以及具有第一和第二端的熔丝链接区域，其中第一端以最接近第一多个触点的预定距离接触阳极区域，而第二端 以与第二多个触点最接近的预定距离接触阴极区域，其中阴极区域小于用于加重电迁移效应的阳极区域。