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    Semiconductor device with split gate memory cell and fabrication method thereof
    3.
    发明授权
    Semiconductor device with split gate memory cell and fabrication method thereof 有权
    具有分离栅极存储单元的半导体器件及其制造方法

    公开(公告)号：US08325516B2

    公开(公告)日：2012-12-04

    申请号：US12603779

    申请日：2009-10-22

    申请人： Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

    发明人： Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

    IPC分类号： G11C11/34

    CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/7881

    摘要： A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.

    摘要翻译： 分离门存储单元。 第一和第二导电类型的第一和第二阱区域形成在衬底中。 浮置栅极设置在第一阱区和第二阱区的接合处并且与衬底绝缘。 控制栅极设置在浮动栅极的侧壁上并与基板和浮动栅极绝缘，并且部分地延伸到浮动栅极的上表面。 在第二阱区中形成第一导电类型的掺杂区域。 第一阱区域和掺杂区域分别用作分裂栅极存储单元的源极和漏极区域。

    Bipolar junction transistors having a fin
    4.
    发明授权
    Bipolar junction transistors having a fin 有权
    具有翅片的双极结晶体管

    公开(公告)号：US08258602B2

    公开(公告)日：2012-09-04

    申请号：US12618425

    申请日：2009-11-13

    申请人： Po-Yao Ke ,  Tao-Wen Chung ,  Shine Chung ,  Fu-Lung Hsueh

    发明人： Po-Yao Ke ,  Tao-Wen Chung ,  Shine Chung ,  Fu-Lung Hsueh

    IPC分类号： H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

    CPC分类号： H01L29/73 ,  H01L21/823431

    摘要： Design and methods for fabricating bipolar junction transistors are described. In one embodiment, a semiconductor device includes a first fin comprising a first emitter region, a first base region, and a first collector region. The first emitter region, the first base region, and the first collector region form a bipolar junction transistor. A second fin is disposed adjacent and parallel to the first fin. The second fin includes a first contact to the first base region.

    摘要翻译： 描述用于制造双极结型晶体管的设计和方法。 在一个实施例中，半导体器件包括包括第一发射极区域，第一基极区域和第一集电极区域的第一鳍片。 第一发射极区域，第一基极区域和第一集电极区域形成双极结型晶体管。 第二翅片邻近并平行于第一翅片设置。 第二鳍片包括与第一基底区域的第一接触。

    Circuit and method for a digital process monitor
    5.
    发明授权
    Circuit and method for a digital process monitor 有权
    数字过程监控的电路和方法

    公开(公告)号：US08183910B2

    公开(公告)日：2012-05-22

    申请号：US12495024

    申请日：2009-06-30

    申请人： Shine Chung ,  Fu-Lung Hsueh

    发明人： Shine Chung ,  Fu-Lung Hsueh

    IPC分类号： H01L35/00 ,  H01L37/00 ,  H03K3/42 ,  H03K17/78

    CPC分类号： G01R31/3004 ,  G01R31/31703

    摘要： A circuit and method for a digital process monitor is disclosed. Circuits for comparing a current or voltage to a current or voltage corresponding to a device having process dependent circuit characteristics are disclosed, having converters for converting current or voltage measurements proportional to the process dependent circuit characteristic to a digital signal and outputting the digital signal for monitoring. The process dependent circuit characteristics may be selected from transistor threshold voltage, transistor saturation current, and temperature dependent quantities. Calibration is performed using digital techniques such as digital filtering and digital signal processing. The digital process monitor circuit may be formed as a scribe line circuit for wafer characterization or placed in an integrated circuit die as a macro. The process monitor circuit may be accessed using probe pads or scan test circuitry. Methods for monitoring process dependent characteristics using digital outputs are disclosed.

    摘要翻译： 公开了一种用于数字处理监视器的电路和方法。 公开了用于将电流或电压与对应于具有过程相关电路特性的器件相对应的电流或电压进行比较的电路，具有用于将与过程相关的电路特性成比例的电流或电压测量值转换为数字信号的转换器，并输出用于监测的数字信号 。 处理相关电路特性可以选自晶体管阈值电压，晶体管饱和电流和温度依赖量。 使用数字滤波和数字信号处理等数字技术进行校准。 数字处理监视电路可以形成为用于晶片表征的划线电路或者作为宏放置在集成电路管芯中。 可以使用探针焊盘或扫描测试电路来访问过程监控电路。 公开了使用数字输出来监视与过程有关的特性的方法。

    Voltage-control oscillator circuits with combined MOS and bipolar device
    7.
    发明授权
    Voltage-control oscillator circuits with combined MOS and bipolar device 有权
    具有组合MOS和双极器件的压控振荡器电路

    公开(公告)号：US07663445B2

    公开(公告)日：2010-02-16

    申请号：US12237187

    申请日：2008-09-24

    申请人： Shine Chung ,  Fu-Lung Hsueh

    发明人： Shine Chung ,  Fu-Lung Hsueh

    IPC分类号： H03B5/12

    CPC分类号： H03B5/1228 ,  H03B5/1203 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/124

    摘要： A voltage controlled oscillator includes: a first merged device having a first bipolar transistor and a first MOS transistor, the first bipolar transistor having a collector sharing a common active area with a source/drain of the first MOS transistor, and an emitter sharing the common active area with another source/drain of the first MOS transistor, a second merged device having a second bipolar transistor and a second MOS transistor, the second bipolar transistor having a collector sharing a common active area with a source/drain of the second MOS transistor, and an emitter sharing the common active area with another source/drain of the second MOS transistor, and a first inductor connected to both the collector of the first bipolar transistor and a base of the second bipolar transistor.

    摘要翻译： 压控振荡器包括：具有第一双极晶体管和第一MOS晶体管的第一合并器件，所述第一双极晶体管具有与第一MOS晶体管的源极/漏极共用公共有效面积的集电极，以及共享公共 具有第一MOS晶体管的另一源/漏极的有源区，具有第二双极晶体管和第二MOS晶体管的第二合并器件，所述第二双极晶体管具有与第二MOS晶体管的源极/漏极共用共用有效面积的集电极 以及与第二MOS晶体管的另一个源极/漏极共用公共有源区域的发射极，以及连接到第一双极晶体管的集电极和第二双极晶体管的基极的第一电感器。

    DIODE AS VOLTAGE DOWN CONVERTER FOR OTP HIGH PROGRAMMING VOLTAGE APPLICATIONS
    8.
    发明申请
    DIODE AS VOLTAGE DOWN CONVERTER FOR OTP HIGH PROGRAMMING VOLTAGE APPLICATIONS 审中-公开
    二极管作为低压转换器用于OTP高度编程电压应用

    公开(公告)号：US20090296448A1

    公开(公告)日：2009-12-03

    申请号：US12367455

    申请日：2009-02-06

    申请人： Fu Lung Hsueh ,  Shine Chung ,  Wen-Kuan Fang

    发明人： Fu Lung Hsueh ,  Shine Chung ,  Wen-Kuan Fang

    IPC分类号： G11C17/06 ,  G11C5/14 ,  G11C17/00 ,  G11C7/00

    CPC分类号： G11C16/30 ,  G11C5/00

    摘要： A voltage down converter for programming a one-time-programmable (OTP) memory comprising is disclosed, the voltage down converter comprises a bonding pad for coupling to a programming power supply, and at least one forward biased diode coupled between the bonding pad and the OTP memory, wherein a programming voltage received by the OTP memory is lowered from the programming power supply by the voltage drop across the forward biased diode.

    摘要翻译： 公开了一种用于对一次可编程（OTP）存储器进行编程的降压转换器，所述降压转换器包括用于耦合到编程电源的接合焊盘，以及耦合在所述接合焊盘和所述接合焊盘之间的至少一个正向偏置二极管 OTP存储器，其中由OTP存储器接收的编程电压通过正向偏置二极管上的电压降从编程电源降低。

    Semiconductor device with split gate memory cell and fabrication method thereof
    9.
    发明授权
    Semiconductor device with split gate memory cell and fabrication method thereof 失效
    具有分离栅极存储单元的半导体器件及其制造方法

    公开(公告)号：US07626224B2

    公开(公告)日：2009-12-01

    申请号：US11531295

    申请日：2006-09-13

    申请人： Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

    发明人： Yue-Der Chih ,  Shine Chung ,  Wen-Ting Chu

    IPC分类号： H01L29/788

    CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/7881

    摘要： A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.

    摘要翻译： 分离门存储单元。 第一和第二导电类型的第一和第二阱区域形成在衬底中。 浮置栅极设置在第一阱区和第二阱区的接合处并且与衬底绝缘。 控制栅极设置在浮动栅极的侧壁上并与基板和浮动栅极绝缘，并且部分延伸到浮动栅极的上表面。 在第二阱区中形成第一导电类型的掺杂区域。 第一阱区域和掺杂区域分别用作分裂栅极存储单元的源极和漏极区域。

    Waveguides in integrated circuits
    10.
    发明授权
    Waveguides in integrated circuits 有权
    集成电路中的波导

    公开(公告)号：US07612638B2

    公开(公告)日：2009-11-03

    申请号：US11486903

    申请日：2006-07-14

    申请人： Shine Chung ,  Fu-Lung Hsueh

    发明人： Shine Chung ,  Fu-Lung Hsueh

    IPC分类号： H01P3/00 ,  H01P3/12 ,  H01P3/14 ,  H01P1/00 ,  H01P1/06

    CPC分类号： H01P3/12 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A waveguide in semiconductor integrated circuit is disclosed, the waveguide comprises a horizontal first metal plate, a horizontal second metal plate above the first metal plate, separated by an insulation material, and a plurality of metal vias positioned in two parallel lines, running vertically through the insulation material in contacts with both the first and second metal plates, wherein the first and second metal plates and the plurality of metal vias form a metal enclosure in a cross-sectional view that can serve as a waveguide.

    摘要翻译： 公开了一种半导体集成电路中的波导，波导包括水平的第一金属板，在第一金属板上方的水平的第二金属板，由绝缘材料隔开，并且多个金属通孔位于两条平行的线上，垂直延伸穿过 所述绝缘材料与所述第一和第二金属板两者接触，其中所述第一和第二金属板和所述多个金属通孔以横截面视图形成可用作波导的金属外壳。