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公开(公告)号：US20090134456A1
公开(公告)日：2009-05-28
申请号：US11921085
申请日：2006-05-25
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/207 , H01L29/0623 , H01L29/0649 , H01L29/0653 , H01L29/2003 , H01L29/66462 , H01L29/7787 , H01L29/7788 , H01L29/7828 , H01L29/7832
摘要： The present invention aims to suppress the diffusion of p-type impurities (typically magnesium), included in a semiconductor region of a III-V compound semiconductor, into an adjoining different semiconductor region. A semiconductor device 10 of the present invention comprises a first semiconductor region 28 of gallium nitride (GaN) including p-type impurities that consist of magnesium, a second semiconductor region 34 of gallium nitride, and an impurity diffusion suppression layer 32 of silicon oxide (SiO2) located between the first semiconductor region 28 and the second semiconductor region 34.
摘要翻译： 本发明旨在抑制包含在III-V族化合物半导体的半导体区域中的p型杂质（通常为镁）扩散到邻接的不同半导体区域中。 本发明的半导体器件10包括由镁构成的p型杂质，氮化镓的第二半导体区域34和氧化硅的杂质扩散抑制层32的氮化镓（GaN）的第一半导体区域28（ SiO 2），位于第一半导体区域28和第二半导体区域34之间。
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公开(公告)号：US09184271B2
公开(公告)日：2015-11-10
申请号：US12822328
申请日：2010-06-24
申请人： Masahiro Sugimoto , Tetsu Kachi , Yoshitaka Nakano , Tsutomu Uesugi , Hiroyuki Ueda , Narumasa Soejima
发明人： Masahiro Sugimoto , Tetsu Kachi , Yoshitaka Nakano , Tsutomu Uesugi , Hiroyuki Ueda , Narumasa Soejima
IPC分类号： H01L29/778 , H01L29/66 , H01L21/28 , H01L29/20
CPC分类号： H01L29/778 , H01L21/28 , H01L29/2003 , H01L29/66431 , H01L29/66462 , H01L29/7787
摘要： A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm−3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.
摘要翻译： 半导体器件具有其中堆叠p-GaN层，SI-GaN层和AlGaN层的堆叠结构，并且具有形成在AlGaN层的顶表面侧的栅电极。 AlGaN层的带隙比p-GaN层和SI-GaN层的带隙宽。 此外，SI-GaN层的杂质浓度小于1×1017cm-3。 包括III-V半导体的半导体器件可以具有稳定的常关断操作。
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公开(公告)号：US20110316049A1
公开(公告)日：2011-12-29
申请号：US13254638
申请日：2009-03-02
IPC分类号： H01L29/778 , H01L21/20
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/41766 , H01L29/66462 , H01L29/7788
摘要： Provided are a vertical nitride semiconductor device in which occurrence of leak currents can be suppressed, and a method for manufacturing such nitride semiconductor device. A nitride semiconductor device, which is a vertical HEMT, is provided with an n− type GaN first nitride semiconductor layer, p+ type GaN second nitride semiconductor layers, an n− type GaN third nitride semiconductor layer, and an n− type AlGaN fourth nitride semiconductor layer that is in hetero junction with a front surface of the third nitride semiconductor layer. Openings that penetrate the third nitride semiconductor layer and reach front surfaces of the second nitride semiconductor layers are provided at positions isolated from the peripheral edge of the third nitride semiconductor layer. Source electrodes are provided in the openings. Etching damage that is in contact with the source electrodes is surrounded by a region where no etching damage is formed.
摘要翻译： 提供了可以抑制泄漏电流的发生的垂直氮化物半导体器件，以及这种氮化物半导体器件的制造方法。 作为垂直HEMT的氮化物半导体器件设置有n型GaN第一氮化物半导体层，p +型GaN第二氮化物半导体层，n型GaN第三氮化物半导体层和n型AlGaN第四氮化物半导体层 半导体层，其与第三氮化物半导体层的前表面处于异质结。 穿过第三氮化物半导体层并到达第二氮化物半导体层的前表面的开口设置在与第三氮化物半导体层的外围边缘隔离的位置处。 源电极设置在开口中。 与源电极接触的蚀刻损伤被没有形成蚀刻损伤的区域包围。
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公开(公告)号：US20080149964A1
公开(公告)日：2008-06-26
申请号：US11795117
申请日：2006-01-20
IPC分类号： H01L29/778
CPC分类号： H01L29/452 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/7787
摘要： A semiconductor device 10 comprises a heterojunction between a lower semiconductor layer 26 made of p-type gallium nitride and an upper semiconductor layer 28 made of n-type AlGaN, wherein the upper semiconductor layer 28 has a larger band gap than the lower semiconductor layer 26. The semiconductor device 10 further comprises a drain electrode 32 formed on a portion of a top surface of the upper semiconductor layer 28, a source electrode 34 formed on a different portion of the top surface of the upper semiconductor layer 28, and a gate electrode 36 electrically connected to the lower semiconductor layer 26. The semiconductor device 10 can operate as normally-off.
摘要翻译： 半导体器件10包括由p型氮化镓制成的下半导体层26和由n型AlGaN制成的上半导体层28之间的异质结，其中上半导体层28具有比下半导体层26更大的带隙 。 半导体器件10还包括形成在上半导体层28的顶表面的一部分上的漏电极32，形成在上半导体层28的顶表面的不同部分上的源极34和栅电极36 电连接到下半导体层26。 半导体器件10可以正常工作。
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公开(公告)号：US20080128862A1
公开(公告)日：2008-06-05
申请号：US11667735
申请日：2005-11-14
CPC分类号： H01L29/7802 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0843 , H01L29/0847 , H01L29/0891 , H01L29/2003 , H01L29/41 , H01L29/778 , H01L29/7788 , H01L29/8122
摘要： A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.
摘要翻译： 半导体器件设置有漏电极22，半导体基板32，覆盖半导体基板32的一部分表面的电流调节层42，并在半导体基板的表面留下未被覆盖的表面55 板32，覆盖电流调节层42的表面的半导体层50和形成在半导体层50的表面的源电极62。 在半导体层50内形成有漂移区56，沟道形成区54和源极区52。 漏电极22连接到电源的第一端子，源电极62连接到电源的第二端子。 利用该半导体层50，可以提高耐压或减少电流泄漏的发生。
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公开(公告)号：US08008749B2
公开(公告)日：2011-08-30
申请号：US11667735
申请日：2005-11-14
IPC分类号： H01L29/20
CPC分类号： H01L29/7802 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0843 , H01L29/0847 , H01L29/0891 , H01L29/2003 , H01L29/41 , H01L29/778 , H01L29/7788 , H01L29/8122
摘要： A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.
摘要翻译： 半导体器件设置有漏电极22，半导体基板32，覆盖半导体基板32的一部分表面的电流调节层42，并在半导体基板的表面留下未被覆盖的表面55 板32，覆盖电流调节层42的表面的半导体层50和形成在半导体层50的表面的源电极62.漂移区56，沟道形成区54和源极区52是 形成在半导体层50内。漏电极22连接到电源的第一端子，源电极62连接到电源的第二端子。 利用该半导体层50，可以提高耐压或减少电流泄漏的发生。
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公开(公告)号：US07800130B2
公开(公告)日：2010-09-21
申请号：US11795117
申请日：2006-01-20
IPC分类号： H01L29/778
CPC分类号： H01L29/452 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/7787
摘要： A semiconductor device 10 comprises a heterojunction between a lower semiconductor layer 26 made of p-type gallium nitride and an upper semiconductor layer 28 made of n-type AlGaN, wherein the upper semiconductor layer 28 has a larger band gap than the lower semiconductor layer 26. The semiconductor device 10 further comprises a drain electrode 32 formed on a portion of a top surface of the upper semiconductor layer 28, a source electrode 34 formed on a different portion of the top surface of the upper semiconductor layer 28, and a gate electrode 36 electrically connected to the lower semiconductor layer 26. The semiconductor device 10 can operate as normally-off.
摘要翻译： 半导体器件10包括由p型氮化镓制成的下半导体层26和由n型AlGaN制成的上半导体层28之间的异质结，其中上半导体层28具有比下半导体层26更大的带隙 半导体器件10还包括形成在上半导体层28的顶表面的一部分上的漏极32，形成在上半导体层28的顶表面的不同部分上的源极34和栅电极 36电连接到下半导体层26.半导体器件10可以正常工作。
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公开(公告)号：US20080073652A1
公开(公告)日：2008-03-27
申请号：US11632665
申请日：2005-06-22
申请人： Masahiro Sugimoto , Tetsu Kachi , Yoshitaka Nakano , Tsutomu Uesugi , Hiroyuki Ueda , Narumasa Soejima
发明人： Masahiro Sugimoto , Tetsu Kachi , Yoshitaka Nakano , Tsutomu Uesugi , Hiroyuki Ueda , Narumasa Soejima
IPC分类号： H01L29/205 , H01L21/338 , H01L29/778
CPC分类号： H01L29/778 , H01L21/28 , H01L29/2003 , H01L29/66431 , H01L29/66462 , H01L29/7787
摘要： The semiconductor device has a stacked structure in which a p-GaN layer 32, an SI-GaN layer 62, and an AlGaN layer 34 are stacked, and has a gate electrode 44 that is formed at a top surface side of the AlGaN layer 34. A band gap of the AlGaN layer 34 is wider than a band gap of the p-GaN layer 32 and the SI-GaN layer 62. Moreover, impurity concentration of the SI-GaN layer 62 is less than 1×1017 cm−3. The semiconductor devices comprising III-V semiconductors that have a stable normally-off operation are realized.
摘要翻译： 半导体器件具有层叠p-GaN层32，SI-GaN层62和AlGaN层34的堆叠结构，并且具有形成在AlGaN层34的顶面侧的栅电极44 AlGaN层34的带隙比p-GaN层32和SI-GaN层62的带隙宽。另外，SI-GaN层62的杂质浓度小于1×10 17 / SUP> cm 3 -3。 实现了具有稳定的常关断操作的包括III-V半导体的半导体器件。
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公开(公告)号：US09543428B2
公开(公告)日：2017-01-10
申请号：US14400365
申请日：2013-06-06
申请人： DENSO CORPORATION , TOYOTA JIDOSHA KABUSHIKI KAISHA , Masahiro Sugimoto , Hidefumi Takaya , Akitaka Soeno , Jun Morimoto
发明人： Yuichi Takeuchi , Naohiro Suzuki , Masahiro Sugimoto , Hidefumi Takaya , Akitaka Soeno , Jun Morimoto , Narumasa Soejima , Yukihiko Watanabe
IPC分类号： H01L29/78 , H01L29/16 , H01L21/82 , H01L29/66 , H01L29/10 , H01L29/872 , H01L21/04 , H01L21/306 , H01L21/308 , H01L29/423 , H01L29/417 , H01L29/06 , H01L29/08 , H01L29/861
CPC分类号： H01L29/7811 , H01L21/046 , H01L21/0475 , H01L21/30604 , H01L21/308 , H01L21/761 , H01L21/8213 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/157 , H01L29/158 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/66068 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
摘要翻译： SiC半导体器件具有包含低浓度区域和填充在形成于单元区域的沟槽中的高浓度区域的p型区域。 由低浓度区域提供p型列，并且由高浓度区域提供p +型深层。 因此，由于可以通过由n型漂移层提供的p型列和n型列来形成SJ结构，所以可以降低导通电阻。 由于漏极电位可以被p +型深层阻挡，所以在关断时，施加到栅极绝缘膜的电场可以减轻，从而可以限制栅极绝缘膜的破裂。 因此，SiC半导体器件可以实现导通电阻的降低和栅极绝缘膜的破损的限制。
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公开(公告)号：US09818860B2
公开(公告)日：2017-11-14
申请号：US15365150
申请日：2016-11-30
申请人： DENSO CORPORATION , TOYOTA JIDOSHA KABUSHIKI KAISHA , Masahiro Sugimoto , Hidefumi Takaya , Akitaka Soeno , Jun Morimoto
发明人： Yuichi Takeuchi , Naohiro Suzuki , Masahiro Sugimoto , Hidefumi Takaya , Akitaka Soeno , Jun Morimoto , Narumasa Soejima , Yukihiko Watanabe
IPC分类号： H01L29/78 , H01L29/16 , H01L21/82 , H01L29/417 , H01L29/66 , H01L29/10 , H01L29/872 , H01L21/04 , H01L21/306 , H01L21/308 , H01L29/423 , H01L21/761 , H01L29/15 , H01L29/06 , H01L29/08 , H01L29/861
CPC分类号： H01L29/7811 , H01L21/046 , H01L21/0475 , H01L21/30604 , H01L21/308 , H01L21/761 , H01L21/8213 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/157 , H01L29/158 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/66068 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
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