公开(公告)号：US06627497B2

公开(公告)日：2003-09-30

申请号：US10162192

申请日：2002-06-05

申请人： Naruhiko Nakanishi ,  Nobuyoshi Kobayashi ,  Yuzuru Ohji ,  Sinpei Iijima ,  Yasuhiro Sugawara ,  Misuzu Kanai

发明人： Naruhiko Nakanishi ,  Nobuyoshi Kobayashi ,  Yuzuru Ohji ,  Sinpei Iijima ,  Yasuhiro Sugawara ,  Misuzu Kanai

IPC分类号： H01L218242

CPC分类号： H01L21/31604 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/56 ,  H01L28/60 ,  H01L28/65

摘要： A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.

公开(公告)号：US06340632B1

公开(公告)日：2002-01-22

申请号：US09585629

申请日：2000-06-02

申请人： Shinichi Fukada ,  Kazuo Nojiri ,  Takashi Yunogami ,  Shoji Hotta ,  Hideo Aoki ,  Takayuki Oshima ,  Nobuyoshi Kobayashi

发明人： Shinichi Fukada ,  Kazuo Nojiri ,  Takashi Yunogami ,  Shoji Hotta ,  Hideo Aoki ,  Takayuki Oshima ,  Nobuyoshi Kobayashi

IPC分类号： H01L214763

CPC分类号： H01L21/76874 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.

摘要翻译： 绝缘膜34至38（其绝缘膜34,36,38是氮化硅膜和绝缘膜35,38是氧化硅膜）依次形成在第四布线层的布线33上，并将凹槽图案40转移到 绝缘膜38。 形成防反射膜41以填充绝缘膜38的槽40，然后形成承载孔图案43的抗蚀剂膜42。 在存在抗蚀剂膜42的情况下对膜进行蚀刻操作，以将孔图案转印到绝缘膜38,37,36和绝缘膜35的一部分中。随后，将抗蚀剂膜42和抗反射膜 41，并且通过使用绝缘膜38作为掩模将槽图案40和孔图案43分别转印到绝缘膜37和绝缘膜35中。

公开(公告)号：US5194939A

公开(公告)日：1993-03-16

申请号：US796378

申请日：1991-11-22

申请人： Nobuyoshi Kobayashi ,  Hisanori Kominami

发明人： Nobuyoshi Kobayashi ,  Hisanori Kominami

IPC分类号： H04N5/92 ,  H03H17/06 ,  H04N5/14 ,  H04N9/804 ,  H04N9/808 ,  H04N19/00 ,  H04N19/423 ,  H04N19/59 ,  H04N19/80

CPC分类号： H03H17/06 ,  H04N9/8042

摘要： A digital video signal processing apparatus for reducing the data rate of, and interpolating digital, video signals of a component format. The apparatus comprises a half-band high pass filter having a coefficient profile equivalent to that obtained by setting a center coefficient of an odd-order half-band low pass filter to zero, or a notch filter having a coefficient profile equivalent to that obtained by eliminating a center coefficient and even-numbered coefficients of such a low pass filter, and a delay line for giving a predetermined delay time to the signal supplied thereto, whereby the data rate of multiplexed or time-divided signals can be reduced, or the signals interpolated, in a relatively simple design employing a single digital filter.

公开(公告)号：US5013526A

公开(公告)日：1991-05-07

申请号：US438596

申请日：1989-11-17

申请人： Nobuyoshi Kobayashi ,  Masayuki Suzuki ,  Seiichi Kondo ,  Makoto Matsui ,  Kiichiro Mukai

发明人： Nobuyoshi Kobayashi ,  Masayuki Suzuki ,  Seiichi Kondo ,  Makoto Matsui ,  Kiichiro Mukai

IPC分类号： C23C14/14 ,  C23C16/06 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/532 ,  H01L39/06 ,  H01L39/12

CPC分类号： H01L23/53285 ,  H01L39/12 ,  H01L2924/0002 ,  Y10S420/901 ,  Y10T428/12528 ,  Y10T428/12806

摘要： A superconducting material made of tungsten or molybdenum containing a specified amount of silicon, a wiring made of this superconducting material, and a semiconductor device using this wiring.The above-mentioned superconducting material undegoes no damage even in the steps of heat treatments effected after the formation of a wiring therefrom by virtue of its high melting point, and can be very easily patterned by reactive ion etching using SF.sub.6 as an etching gas, which has heretofore been generally employed. These features, in which conventional superconducting materials are lacking, allow the superconducting material of the present invention to exhibit excellent properties particularly when used in the wirings of a semiconductor device.

公开(公告)号：US08187981B2

公开(公告)日：2012-05-29

申请号：US11870641

申请日：2007-10-11

申请人： Kazuhiro Tomioka ,  Nobuyoshi Kobayashi ,  Isamu Sakuragi ,  Kazuhiro Kubota

发明人： Kazuhiro Tomioka ,  Nobuyoshi Kobayashi ,  Isamu Sakuragi ,  Kazuhiro Kubota

IPC分类号： H01L21/302

CPC分类号： H01L21/31138 ,  G03F7/427 ,  H01L21/31058 ,  H01L21/76814 ,  H01L21/76831

摘要： A substrate processing method includes preparing a substrate having a low-k interlayer dielectric film as a to-be-etched film and a photoresist film, formed on the low-k interlayer insulating film, serving as an etching mask with a predetermined circuit pattern; etching the low-k interlayer insulating film through the photoresist film to form grooves and/or holes in the low-k interlayer insulating film; ashing the photoresist film by using hydrogen radicals generated by bring a hydrogen-containing gas into contact with a catalyst of a high temperature; and recovering damage to the low-k interlayer insulating film due to the ashing by supplying a specific recovery gas. The method further includes recovering damage to the low-k interlayer insulating film due to the etching by supplying a specific recovery gas.

摘要翻译： 基板处理方法包括：在低k层间绝缘膜上形成具有预定电路图案的蚀刻掩模的低k层间绝缘膜作为被蚀刻膜和光致抗蚀剂膜的基板; 通过光致抗蚀剂膜蚀刻低k层间绝缘膜，以在低k层间绝缘膜中形成凹槽和/或孔; 使用通过使含氢气体与高温催化剂接触而产生的氢自由基来使光致抗蚀剂膜发生灰化; 并且通过供给特定的回收气体，由于灰化而恢复对低k层间绝缘膜的损坏。 该方法还包括通过提供特定的回收气体来回收由于蚀刻而导致的低k层间绝缘膜的损坏。

公开(公告)号：US20110231000A1

公开(公告)日：2011-09-22

申请号：US13131755

申请日：2009-10-23

申请人： Syunsuke Higashi ,  Nobuyoshi Kobayashi ,  Yasuyuki Nishihara ,  Masaya Matsumoto

发明人： Syunsuke Higashi ,  Nobuyoshi Kobayashi ,  Yasuyuki Nishihara ,  Masaya Matsumoto

IPC分类号： G06F1/28 ,  G06F19/00

CPC分类号： H05K13/0885

摘要： A power monitoring device is configured to monitor power consumed in a device for mounting component, which constitutes a component mounting line. The power monitoring device includes: an operation information collecting section configured to collect in time-series operation information representing a device operation state of the device for mounting component and to create time-series data of the operation information; a power measuring section configured to measure in time-series an amount of power consumption representing an amount of power consumed in the device for mounting component and to create time-series data of the amount of power; a synchronous output section configured to output the time-series data of the operation information and the time-series data of the amount of power by synchronizing respective time axes in time-series with each other.

摘要翻译： 功率监视装置被配置为监视构成部件安装线的用于安装部件的装置中消耗的功率。 电力监视装置包括：操作信息收集部，被配置为收集表示用于安装部件的装置的装置运行状态的时间序列运算信息，并生成运算信息的时间序列数据; 功率测量部件，被配置为测量表示在用于安装部件的装置中消耗的功率量的功率消耗量，并且产生功率量的时间序列数据; 同步输出部，被配置为通过使时间轴彼此同步各个时间轴来输出操作信息的时间序列数据和功率量的时间序列数据。

公开(公告)号：US20100124618A1

公开(公告)日：2010-05-20

申请号：US12618419

申请日：2009-11-13

申请人： Akiko Kobayashi ,  Akira Shimizu ,  Kuo-wei Hong ,  Nobuyoshi Kobayashi ,  Atsuki Fukazawa

发明人： Akiko Kobayashi ,  Akira Shimizu ,  Kuo-wei Hong ,  Nobuyoshi Kobayashi ,  Atsuki Fukazawa

IPC分类号： B05D3/04

CPC分类号： C23C16/45542 ,  C23C16/345 ,  C23C16/56

摘要： A film forming cycle based on pulse CVD or ALD is repeated multiple times to form a single layer of insulation film, while a reforming cycle is implemented in the aforementioned process, either once or multiple times per each film forming cycle, by treating the surface of formed film using a treating gas that has been activated by a plasma.

摘要翻译： 基于脉冲CVD或ALD的成膜循环重复多次以形成单层绝缘膜，而在上述过程中重整循环是每个成膜循环一次或多次，通过处理 使用已经被等离子体激活的处理气体形成膜。

公开(公告)号：US06423992B1

公开(公告)日：2002-07-23

申请号：US09854569

申请日：2001-05-15

申请人： Takuya Fukuda ,  Yuzuru Ohji ,  Nobuyoshi Kobayashi

发明人： Takuya Fukuda ,  Yuzuru Ohji ,  Nobuyoshi Kobayashi

IPC分类号： H01L2976

摘要： A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.

公开(公告)号：US06303478B1

公开(公告)日：2001-10-16

申请号：US09421125

申请日：1999-10-19

申请人： Yoshitaka Nakamura ,  Nobuyoshi Kobayashi ,  Takuya Fukuda ,  Masayoshi Saito

发明人： Yoshitaka Nakamura ,  Nobuyoshi Kobayashi ,  Takuya Fukuda ,  Masayoshi Saito

IPC分类号： H01L218242

CPC分类号： H01L27/10844 ,  H01L21/768 ,  H01L27/105 ,  H01L27/10808 ,  H01L27/10852

摘要： A method of fabricating a semiconductor device having, for example, a memory cell array portion and a peripheral circuit portion is disclosed. By such a method, a first interlayer insulating film is formed on a semiconductor substrate, a first connection hole is formed by selectively removing a predetermined portion of the first interlayer insulating film, the sides of the first hole being substantially vertical to the bottom thereof, a first plug is formed by padding the first hole with a metallic film and, subsequently, a second interlayer insulating film is formed on the first insulating film, a second hole is formed by selectively removing a predetermined portion of the second interlayer insulating film, the sides of the second hole being substantially vertical to the bottom thereof, and a second plug aligned to be in direct connection with the first plug is formed by padding the second hole with the metallic film. A MOS transistor is formed on the semiconductor substrate before the first interlayer insulating film is formed and the first hole formed is extended to expose the diffused layer of the MOS transistor. The surfaces of both the first and second interlayer insulating films are smoothed by a chemical mechanical polishing (CMP) method. The process of padding the connection holes with the metallic film is effected through a CVD or selective CVD method.

摘要翻译： 公开了一种制造具有例如存储单元阵列部分和外围电路部分的半导体器件的方法。 通过这样的方法，在半导体衬底上形成第一层间绝缘膜，通过选择性地去除第一层间绝缘膜的预定部分，第一孔的侧面基本垂直于其底部而形成第一连接孔， 通过用金属膜填充第一孔而形成第一插塞，随后在第一绝缘膜上形成第二层间绝缘膜，通过选择性地去除第二层间绝缘膜的预定部分形成第二孔， 第二孔的侧面基本上垂直于其底部，并且通过用金属膜填充第二孔而形成与第一塞直接连接的第二塞子。 在形成第一层间绝缘膜之前，在半导体衬底上形成MOS晶体管，并且形成的第一孔延伸以露出MOS晶体管的扩散层。 通过化学机械抛光（CMP）方法使第一和第二层间绝缘膜的表面平滑。 用金属膜填充连接孔的过程通过CVD或选择性CVD方法进行。

公开(公告)号：US5307157A

公开(公告)日：1994-04-26

申请号：US021521

申请日：1993-02-23

申请人： Nobuyoshi Kobayashi ,  Hisanori Kominami

发明人： Nobuyoshi Kobayashi ,  Hisanori Kominami

IPC分类号： H04N5/92 ,  H03H17/06 ,  H04N5/14 ,  H04N9/804 ,  H04N9/808 ,  H04N19/00 ,  H04N19/423 ,  H04N19/59 ,  H04N19/80 ,  H04N9/64

CPC分类号： H03H17/06 ,  H04N9/8042

摘要： A digital video signal processing apparatus for reducing the data rate of, and interpolating digital, video signals of a component format. The apparatus comprises a half-band high pass filter having a coefficient profile equivalent to that obtained by setting a center coefficient of an odd-order half-band low pass filter to zero, or a notch filter having a coefficient profile equivalent to that obtained by eliminating a center coefficient and even-numbered coefficients of such a low pass filter, and a delay line for giving a predetermined delay time to the signal supplied thereto, whereby the data rate of multiplexed or time-divided signals can be reduced, or the signals interpolated, in a relatively simple design employing a single digital filter.

摘要翻译： 一种用于降低分量格式的数字速率和内插数字视频信号的数字视频信号处理装置。 该装置包括具有等于通过将奇数半频带低通滤波器的中心系数设置为零而获得的系数分布的半带高通滤波器，或具有等于由 消除这种低通滤波器的中心系数和偶数系数，以及用于给予其提供的信号预定的延迟时间的延迟线，从而可以减少多路复用或分时信号的数据速率，或者信号 以采用单个数字滤波器的相对简单的设计进行内插。