公开(公告)号：US06432769B1

公开(公告)日：2002-08-13

申请号：US09642582

申请日：2000-08-22

申请人： Takuya Fukuda ,  Nobuyoshi Kobayashi ,  Yoshitaka Nakamura ,  Masayoshi Saito ,  Shinichi Fukada ,  Yoshifumi Kawamoto

发明人： Takuya Fukuda ,  Nobuyoshi Kobayashi ,  Yoshitaka Nakamura ,  Masayoshi Saito ,  Shinichi Fukada ,  Yoshifumi Kawamoto

IPC分类号： H01L2972

CPC分类号： H01L27/10808 ,  H01L27/108

摘要： The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

摘要翻译： 存储单元的新结构能够在不增加处理次数的情况下避免步骤的问题，制造过程中同一基板的公共部分增加的半导体集成电路的结构和半导体的结构 公开了不增加处理次数的环境障碍措施的集成电路。 采用通过将电容器的存储节点经由插头和焊盘连接到扩散层，在多个金属布线层的最上层形成电容器的存储单元结构。 最好将形成在最上层的金属布线层中的电介质膜和由存储节点和平板电极构成的辅助电容器连接到电容器。 还希望电容器的平板电极覆盖芯片。

公开(公告)号：US06303478B1

公开(公告)日：2001-10-16

申请号：US09421125

申请日：1999-10-19

申请人： Yoshitaka Nakamura ,  Nobuyoshi Kobayashi ,  Takuya Fukuda ,  Masayoshi Saito

发明人： Yoshitaka Nakamura ,  Nobuyoshi Kobayashi ,  Takuya Fukuda ,  Masayoshi Saito

IPC分类号： H01L218242

CPC分类号： H01L27/10844 ,  H01L21/768 ,  H01L27/105 ,  H01L27/10808 ,  H01L27/10852

摘要： A method of fabricating a semiconductor device having, for example, a memory cell array portion and a peripheral circuit portion is disclosed. By such a method, a first interlayer insulating film is formed on a semiconductor substrate, a first connection hole is formed by selectively removing a predetermined portion of the first interlayer insulating film, the sides of the first hole being substantially vertical to the bottom thereof, a first plug is formed by padding the first hole with a metallic film and, subsequently, a second interlayer insulating film is formed on the first insulating film, a second hole is formed by selectively removing a predetermined portion of the second interlayer insulating film, the sides of the second hole being substantially vertical to the bottom thereof, and a second plug aligned to be in direct connection with the first plug is formed by padding the second hole with the metallic film. A MOS transistor is formed on the semiconductor substrate before the first interlayer insulating film is formed and the first hole formed is extended to expose the diffused layer of the MOS transistor. The surfaces of both the first and second interlayer insulating films are smoothed by a chemical mechanical polishing (CMP) method. The process of padding the connection holes with the metallic film is effected through a CVD or selective CVD method.

摘要翻译： 公开了一种制造具有例如存储单元阵列部分和外围电路部分的半导体器件的方法。 通过这样的方法，在半导体衬底上形成第一层间绝缘膜，通过选择性地去除第一层间绝缘膜的预定部分，第一孔的侧面基本垂直于其底部而形成第一连接孔， 通过用金属膜填充第一孔而形成第一插塞，随后在第一绝缘膜上形成第二层间绝缘膜，通过选择性地去除第二层间绝缘膜的预定部分形成第二孔， 第二孔的侧面基本上垂直于其底部，并且通过用金属膜填充第二孔而形成与第一塞直接连接的第二塞子。 在形成第一层间绝缘膜之前，在半导体衬底上形成MOS晶体管，并且形成的第一孔延伸以露出MOS晶体管的扩散层。 通过化学机械抛光（CMP）方法使第一和第二层间绝缘膜的表面平滑。 用金属膜填充连接孔的过程通过CVD或选择性CVD方法进行。

公开(公告)号：US06479899B1

公开(公告)日：2002-11-12

申请号：US09051978

申请日：1998-04-24

申请人： Takuya Fukuda ,  Nobuyoshi Kobayashi ,  Yoshitaka Nakamura ,  Masayoshi Saito ,  Shinichi Fukada ,  Yoshifumi Kawamoto

发明人： Takuya Fukuda ,  Nobuyoshi Kobayashi ,  Yoshitaka Nakamura ,  Masayoshi Saito ,  Shinichi Fukada ,  Yoshifumi Kawamoto

IPC分类号： H01L2348

CPC分类号： H01L27/10808 ,  H01L27/108

摘要： The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

公开(公告)号：US06700152B2

公开(公告)日：2004-03-02

申请号：US10231053

申请日：2002-08-30

申请人： Takuya Fukuda ,  Nobuyoshi Kobayashi ,  Yoshitaka Nakamura ,  Masayoshi Saito ,  Shinichi Fukada ,  Yoshifumi Kawamoto

发明人： Takuya Fukuda ,  Nobuyoshi Kobayashi ,  Yoshitaka Nakamura ,  Masayoshi Saito ,  Shinichi Fukada ,  Yoshifumi Kawamoto

IPC分类号： H01L27108

CPC分类号： H01L27/10808 ,  H01L27/108

摘要： The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

摘要翻译： 存储单元的新结构能够在不增加处理次数的情况下避免步骤的问题，制造过程中同一基板的公共部分增加的半导体集成电路的结构和半导体的结构 公开了不增加处理次数的环境障碍措施的集成电路。 采用通过将电容器的存储节点经由插头和焊盘连接到扩散层，在多个金属布线层的最上层形成电容器的存储单元结构。 最好将形成在最上层的金属布线层中的电介质膜和由存储节点和平板电极构成的辅助电容器连接到电容器。 还希望电容器的平板电极覆盖芯片。

公开(公告)号：US5986299A

公开(公告)日：1999-11-16

申请号：US962730

申请日：1997-11-03

申请人： Yoshitaka Nakamura ,  Nobuyoshi Kobayashi ,  Takuya Fukuda ,  Masayoshi Saito

发明人： Yoshitaka Nakamura ,  Nobuyoshi Kobayashi ,  Takuya Fukuda ,  Masayoshi Saito

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10844 ,  H01L21/768 ,  H01L27/105 ,  H01L27/10808 ,  H01L27/10852

摘要： A semiconductor integrated circuit device of the invention is provided with a memory cell array portion and a peripheral circuit portions. In the memory cell array portion, a plurality of plugs which penetrate each of a plurality of interlayer insulating films and the sides of which are almost vertical are directly connected in sequence. In the peripheral circuit portion, a plurality of plugs are mutually connected through contact pads for wiring.

摘要翻译： 本发明的半导体集成电路器件具有存储单元阵列部分和外围电路部分。 在存储单元阵列部分中，贯穿多个层间绝缘膜中的每一个并且其侧面几乎垂直的多个插头依次直接连接。 在外围电路部分中，多个插头通过用于布线的接触垫相互连接。

公开(公告)号：US06423992B1

公开(公告)日：2002-07-23

申请号：US09854569

申请日：2001-05-15

申请人： Takuya Fukuda ,  Yuzuru Ohji ,  Nobuyoshi Kobayashi

发明人： Takuya Fukuda ,  Yuzuru Ohji ,  Nobuyoshi Kobayashi

IPC分类号： H01L2976

摘要： A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.

公开(公告)号：US06255151B1

公开(公告)日：2001-07-03

申请号：US09209013

申请日：1998-12-11

申请人： Takuya Fukuda ,  Yuzuru Ohji ,  Nobuyoshi Kobayashi

发明人： Takuya Fukuda ,  Yuzuru Ohji ,  Nobuyoshi Kobayashi

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L21/31053 ,  H01L23/53228 ,  H01L27/10814 ,  H01L27/10882 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.

摘要翻译： 由电容器C引起的存储单元阵列区域和外围电路区域之间的阶梯状偏移通过具有基本上等于电容器C的高度的厚度的绝缘膜而减小。布线或互连槽限定在 通过CMP方法将表面平坦化的绝缘膜的表面附近。 此外，连接孔分别限定在互连槽的底面的下部。 包含铜的第二层互连形成在互连槽内，并且在连接孔内形成包含铜的连接部分。 第二层互连和第一层互连通过缩短长度的连接部彼此连接。 第二层互连和连接部分通过使用CMP方法的镶嵌方法一体地形成。

公开(公告)号：US5177589A

公开(公告)日：1993-01-05

申请号：US765310

申请日：1991-09-25

申请人： Nobuyoshi Kobayashi ,  Hidekazu Goto ,  Masayuki Suzuki ,  Yoshio Homma ,  Natsuki Yokoyama ,  Yoshitaka Nakamura

发明人： Nobuyoshi Kobayashi ,  Hidekazu Goto ,  Masayuki Suzuki ,  Yoshio Homma ,  Natsuki Yokoyama ,  Yoshitaka Nakamura

IPC分类号： C23C16/14 ,  C23C16/42 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768

CPC分类号： H01L21/76876 ,  C23C16/14 ,  C23C16/42 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76843 ,  H01L21/76877 ,  H01L2924/0002

摘要： In forming a metal or metal silicide film by CVD, a fluoro-silane is used as a reaction gas, or a fluoro-silane is added to a source gas. Examples of the metal halide used in the present invention include fluorides and chlorides of tungsten, molybdenum, titanium, tantalum and niobium. Among them, fluorides of tungsten and molybdenum are more desirable particularly from the viewpoint of the availability of the deposited metal or metal silicide. It is preferred that the source gases, i.e. silane series gas and metal halide, be diluted with a carrier gas such as nitrogen, hydrogen, helium or argon, and this is also true of the fluoro-silane. The total pressure is preferably 0.01 to 10 Torr. The reaction temperature is desirably 200.degree. to 800.degree. C., more desirably 300.degree. to 500.degree. C. Plasma CVD instead of thermal CVD may be employed for the purpose of lowering the reaction temperature.

摘要翻译： 在通过CVD形成金属或金属硅化物膜时，使用氟硅烷作为反应气体，或者在源气体中加入氟硅烷。 用于本发明的金属卤化物的实例包括钨，钼，钛，钽和铌的氟化物和氯化物。 其中，特别是从沉积的金属或金属硅化物的可用性的观点出发，更优选钨和钼的氟化物。 优选的原料气体，即硅烷系列气体和金属卤化物，用载气如氮气，氢气，氦气或氩气稀释，氟硅烷也是如此。 总压力优选为0.01〜10托。 反应温度优选为200〜800℃，更优选为300〜500℃。为了降低反应温度，可以使用等离子体CVD代替热CVD。

公开(公告)号：US06686619B2

公开(公告)日：2004-02-03

申请号：US10137426

申请日：2002-05-03

申请人： Yoshitaka Nakamura ,  Hideo Aoki ,  Yoshikazu Ohira ,  Tadashi Umezawa ,  Satoru Yamada ,  Keizou Kawakita ,  Isamu Asano ,  Naoki Fukuda ,  Tsuyoshi Tamaru ,  Hidekazu Goto ,  Nobuyoshi Kobayashi

发明人： Yoshitaka Nakamura ,  Hideo Aoki ,  Yoshikazu Ohira ,  Tadashi Umezawa ,  Satoru Yamada ,  Keizou Kawakita ,  Isamu Asano ,  Naoki Fukuda ,  Tsuyoshi Tamaru ,  Hidekazu Goto ,  Nobuyoshi Kobayashi

IPC分类号： H01L27108

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76889 ,  H01L21/76897 ,  H01L27/10885 ,  H01L28/91 ,  Y10S257/908

摘要： A semiconductor integrated circuit device and a manufacturing method therefor provide advantages that undulations are prevented from being produced in polycrystal silicon plugs in bit line contact holes and that the undesired phenomenon of transversally etching silicide film at contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines formed when forming a first wiring layer are made of a laminate film having a titanium film, a titanium nitride film and a tungsten film, and a titanium silicide film containing nitrogen or oxygen is formed in contact areas of the bit lines and plugs. A titanium silicide film containing nitrogen or oxygen is also formed in contact areas of the first wiring layer and semiconductor substrate. The titanium silicide film may be replaced by silicide film containing nitrogen or oxygen, cobalt silicide film containing nitrogen or oxygen or cobalt silicide film.

摘要翻译： 一种半导体集成电路器件及其制造方法，提供了防止在位线接触孔中的多晶硅插塞中产生起伏的优点，并且在位线和多晶硅插头的触点处横向蚀刻硅化物膜的不期望的现象是 避免。 在形成第一布线层时形成的位线由具有钛膜，氮化钛膜和钨膜的层叠膜制成，并且在位线和插塞的接触区域中形成含有氮或氧的硅化钛膜 。 含有氮或氧的硅化钛膜也形成在第一布线层和半导体衬底的接触区域中。 硅化钛膜可以由含有氮或氧的硅化物膜，含有氮的硅化钴膜或氧化硅或硅化钴膜代替。

公开(公告)号：US06329681B1

公开(公告)日：2001-12-11

申请号：US09215270

申请日：1998-12-18

申请人： Yoshitaka Nakamura ,  Hideo Aoki ,  Yoshikazu Ohira ,  Tadashi Umezawa ,  Satoru Yamada ,  Keizou Kawakita ,  Isamu Asano ,  Naoki Fukuda ,  Tsuyoshi Tamaru ,  Hidekazu Goto ,  Nobuyoshi Kobayashi

发明人： Yoshitaka Nakamura ,  Hideo Aoki ,  Yoshikazu Ohira ,  Tadashi Umezawa ,  Satoru Yamada ,  Keizou Kawakita ,  Isamu Asano ,  Naoki Fukuda ,  Tsuyoshi Tamaru ,  Hidekazu Goto ,  Nobuyoshi Kobayashi

IPC分类号： H01L27108

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76889 ,  H01L21/76897 ,  H01L27/10885 ,  H01L28/91 ,  Y10S257/908

摘要： A semiconductor integrated circuit device and a method of manufacturing such a device provides the advantages that undulations are prevented from being produced in the polycrystal silicon plugs in the bit line contact holes and that the undesired phenomenon of transversally etching the silicide film at the contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines BL formed at the time of forming a first wiring layer 18 is made of a laminate film having a titanium film 18a, a titanium nitride film 18b and a tungsten film 18c and a titanium silicide film 20 containing nitrogen or oxygen is formed in the contact areas of the bit lines BL and the plugs 19. A titanium silicide film 20 containing nitrogen or oxygen is also formed in the contact areas of the first wiring layer 18 and the semiconductor substrate 1. The titanium silicide film 20 may be replaced by a tungsten silicide film containing nitrogen or oxygen, a cobalt silicide film containing nitrogen or oxygen or a cobalt silicide film.

摘要翻译： 半导体集成电路器件和这种器件的制造方法提供了这样的优点：防止在位线接触孔中的多晶硅插塞中产生起伏，并且在触点处的触点处横向蚀刻硅化物膜的不期望的现象 避免了位线和多晶硅插头。 在形成第一布线层18时形成的位线BL由具有钛膜18a，氮化钛膜18b和钨膜18c的层压膜和含有氮或氧的硅化钛膜20形成 位线BL和插头19的接触面积。也可以在第一布线层18和半导体衬底1的接触区域中形成含有氮或氧的硅化钛膜20.硅化钛膜20可以由 含有氮或氧的硅化钨膜，含有氮或氧的硅化钴膜或硅化钴膜。