公开(公告)号：US20100069351A1

公开(公告)日：2010-03-18

申请号：US12449320

申请日：2008-02-05

申请人： Takahiko Taniguchi ,  Kenichi Miyata ,  Osamu Kubo

发明人： Takahiko Taniguchi ,  Kenichi Miyata ,  Osamu Kubo

IPC分类号： A61K31/397 ,  C07D237/02 ,  A61K31/50 ,  C07D265/12 ,  A61K31/537 ,  C07D239/72 ,  A61K31/527 ,  C07D245/04 ,  A61P3/00 ,  A61P9/00

CPC分类号： C07D401/04 ,  C07D409/14 ,  C07D417/14 ,  C07D471/10 ,  C07D487/10 ,  C07D491/107 ,  C07D498/10

摘要： The present invention aims to provide a novel SCD inhibitor.The present invention relate to SCD inhibitor comprising A compound represented by the formula (I) wherein R is an optionally substituted cyclic group or an optionally substituted carbamoyl group, provided that R is not an optionally substituted 7-pyrido[2,3-d]pyrimidyl group; ring A is an optionally further substituted pyridazine ring; R1, R2, R3, R4, R11, R12, R13 and R14 are each independently a hydrogen atom or a substituent, or R1 and R11 in combination, R2 and R12 in combination, R3 and R13 in combination, or R4 and R14 in combination optionally form an oxo group, or R2 and R4 in combination optionally form a bond or an alkylene cross-linkage; m and n are each independently an integer of 0 to 2; ring B is an optionally substituted ring, provided that the two atoms constituting ring B, which are adjacent to the spiro carbon atom, are not oxygen atoms at the same time, or a salt thereof, or a prodrug thereof.

摘要翻译： 本发明旨在提供一种新型的SCD抑制剂。 本发明涉及包含由式（I）表示的化合物的SCD抑制剂，其中R是任选取代的环状基团或任选取代的氨基甲酰基，条件是R不是任选取代的7-吡啶并[2,3-d] 嘧啶基; 环A是任选进一步取代的哒嗪环; R 1，R 2，R 3，R 4，R 11，R 12，R 13和R 14各自独立地为氢原子或取代基，或R 1和R 11组合，R 2和R 12组合，R 3和R 13组合，或R 4和R 14组合 任选地形成氧代基团，或者R 2和R 4组合任选地形成键或亚烷基交联; m和n各自独立地为0〜2的整数。 环B是任选取代的环，条件是与螺环碳原子相邻的构成环B的两个原子不是同时为氧原子，或其盐或其前药。

公开(公告)号：US20090099976A1

公开(公告)日：2009-04-16

申请号：US12240903

申请日：2008-09-29

申请人： Shigeru Kawamoto ,  Yasuhiro Kobayashi ,  Masanori Takamoto ,  Osamu Kubo ,  Takeshi Yokota ,  Yuuji Ide

发明人： Shigeru Kawamoto ,  Yasuhiro Kobayashi ,  Masanori Takamoto ,  Osamu Kubo ,  Takeshi Yokota ,  Yuuji Ide

IPC分类号： G06Q40/00 ,  G06Q90/00

CPC分类号： G06Q40/02 ,  G06Q40/06

摘要： An optimal portfolio determining method enables high speed determination of objective financial product which optimize availability for institutional buyer or retail investor and purchasing amount on the basis of information relating to earning rate or the like of individual name and information relating to information factors influencing for earning rate, and a system for realizing the method. The method includes input step of inputting constraint parameters forming constraint condition for optimizing objective function consisted of an expected value of the earning rate of each individual financial product, individual floating factor as unique factor of each individual financial product influencing for earning, common floating factor as factor influencing for earning of overall financial products, and risk influencing for earning rate and earning of overall financial product, and solving step of determining financial product to perchance and purchasing amount for maximizing the objective function on the basis of input data.

摘要翻译： 最佳投资组合确定方法可以根据影响收益率的信息因素的个人名称和信息的收益率等相关信息，对客观金融产品进行高速度确定，从而优化机构买方或零售投资者的可获得性和采购金额。 ，以及实现该方法的系统。 该方法包括输入约束参数的输入步骤，形成约束条件，用于优化目标函数，包括每个单独金融产品的收益率的预期值，个体浮动因素作为影响收益的每个个体金融产品的独特因素，共同浮动因素为 影响整体金融产品收益的因素，影响整体金融产品收益率和收益的风险，以及根据输入数据，最大化目标函数，确定金融产品确定和采购金额的步骤。

公开(公告)号：US07323771B2

公开(公告)日：2008-01-29

申请号：US11475936

申请日：2006-06-28

申请人： Ryo Fujita ,  Osamu Kubo ,  Kouki Noguchi ,  Masaharu Kubo ,  Michihiro Mishima ,  Yasuhiko Takahashi

发明人： Ryo Fujita ,  Osamu Kubo ,  Kouki Noguchi ,  Masaharu Kubo ,  Michihiro Mishima ,  Yasuhiko Takahashi

IPC分类号： H01L23/52

CPC分类号： G06F11/261 ,  G06F11/267 ,  G06F15/7867 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

摘要： An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

公开(公告)号：US20060237835A1

公开(公告)日：2006-10-26

申请号：US11475961

申请日：2006-06-28

申请人： Ryo Fujita ,  Osamu Kubo ,  Kouki Noguchi ,  Masaharu Kubo ,  Michihiro Mishima ,  Yasuhiko Takahashi

发明人： Ryo Fujita ,  Osamu Kubo ,  Kouki Noguchi ,  Masaharu Kubo ,  Michihiro Mishima ,  Yasuhiko Takahashi

IPC分类号： H01L23/52

CPC分类号： G06F11/261 ,  G06F11/267 ,  G06F15/7867 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

摘要： An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

公开(公告)号：US06989600B2

公开(公告)日：2006-01-24

申请号：US10240651

申请日：2001-03-30

申请人： Masaharu Kubo ,  Ichiro Anjo ,  Akira Nagai ,  Osamu Kubo ,  Hiromi Abe ,  Hitoshi Akamine

发明人： Masaharu Kubo ,  Ichiro Anjo ,  Akira Nagai ,  Osamu Kubo ,  Hiromi Abe ,  Hitoshi Akamine

IPC分类号： H01L23/48

CPC分类号： H01L24/12 ,  H01L21/76838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01044 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014

摘要： CMOS logic LSI comprises, as a part thereof, n-channel MISFET's (Qn), p-channel MISFET's (Qp) and a first-layer wiring (11) to a third-layer (13) formed on a main surface of a silicon substrate (1), and as another part, a fourth-layer wiring (14) to a seventh-layer wiring (17) formed on a main surface of a glass substrate (30) different from the silicon substrate (1). The main surface of the silicon substrate (1) and the main surface of the glass substrate (30) are arranged in face-to-face relation with each other, and a plurality of microbumps (20A) formed at the uppermost portion of the silicon substrate (1) and a plurality of microbumps (20B) formed at the uppermost portion of the glass substrate (30) are electrically connected, thereby constituting the CMOS logic LSI as a whole.

摘要翻译： CMOS逻辑LSI的一部分包括形成在硅的主表面上的n沟道MISFET（Qn），p沟道MISFET（Qp）和第一层布线（11）到第三层（13） 基板（1），另一部分形成在与硅基板（1）不同的玻璃基板（30）的主面上形成的第七层布线（17）。 硅基板（1）的主表面和玻璃基板（30）的主表面彼此面对面地布置，并且形成在所述玻璃基板的最上部的多个微丸（20A） 硅基板（1）和形成在玻璃基板（30）的最上部的多个微胶片（20A）电连接，从而构成整体上的CMOS逻辑LSI。

公开(公告)号：US20060010055A1

公开(公告)日：2006-01-12

申请号：US10975401

申请日：2004-10-29

申请人： Mayumi Morita ,  Tomohiro Umezawa ,  Osamu Kubo

发明人： Mayumi Morita ,  Tomohiro Umezawa ,  Osamu Kubo

IPC分类号： G06Q40/00

CPC分类号： G06Q30/02 ,  G06Q40/00

摘要： A method and an apparatus for easily and efficiently setting an evaluation index suitable for an evaluation purpose when a business or a business portfolio is evaluated. In the method and apparatus, investment distribution is easily and visually confirmed during computation of the evaluation index when an object to be computed is the business portfolio. A table for defining a computation expression model for the evaluation index and a correspondence relationship between the evaluation index and the evaluation purpose is managed by a database to extract and provide an evaluation index model conforming to the evaluation purpose specified by a user. When the business portfolio is evaluated, business investment distributions are represented by a pie chart. The investment distribution information is updated and the evaluation index is computed, by adjusting a distribution surface of the represented pie chart.

摘要翻译： 一种方法和装置，用于在评估业务或业务组合时，容易且有效地设置适于评估目的的评估指标。 在该方法和装置中，当要计算的对象是业务组合时，投资分配在计算评估指数期间容易且可视地确认。 用于定义用于评价指标的计算表达式模型的表和评估指标与评估目的之间的对应关系由数据库管理以提取并提供符合用户指定的评估目的的评估指数模型。 当业务组合被评估时，商业投资分配由饼图表示。 更新投资分配信息，并通过调整表示的饼图的分布面来计算评价指标。

公开(公告)号：US5077146A

公开(公告)日：1991-12-31

申请号：US250576

申请日：1988-09-29

申请人： Osamu Kubo ,  Tutomu Nomura ,  Tadashi Ido ,  Hirotaka Yokoyama

发明人： Osamu Kubo ,  Tutomu Nomura ,  Tadashi Ido ,  Hirotaka Yokoyama

IPC分类号： G11B5/706

CPC分类号： G11B5/70678 ,  Y10S428/90

摘要： Disclosed is a magnetic powder for high-density magnetic recording, formed of a substituted hexagonal ferrite possessing an average particle diameter in the range of 0.01 to 0.2 .mu.m and a coercivity in the range of 200 to 2,000 Oe and characterized by the fact that the substituted hexagonal ferrite has at least 0.05 to 0.5 atom of at least one element selected from the group consisting of Zr and Hf per chemical formula and at least one element selected from among the elements other than Zr and Hf substituted for part of the Fe atom of the ferrite, and a magnetic recording medium of the present invention comprises a substrate and the magnetic powder mentioned above deposited on the substrate. Since the magnetic powder comprises very minute particles, the magnetic powder and the magnetic recording medium are capable of high-density recording. The magnetic powder has an improved desirably controlled aspect ratio for orientation and the temperature characteristic of coercivity (Hc) as compared with the countertype formed of a hexagonal ferrite which has neither Zr nor Hf substituted for the Fe atom.

公开(公告)号：US4636433A

公开(公告)日：1987-01-13

申请号：US795130

申请日：1985-11-05

申请人： Osamu Kubo ,  Tutomu Nomura ,  Tadashi Ido ,  Hirotaka Yokoyama

发明人： Osamu Kubo ,  Tutomu Nomura ,  Tadashi Ido ,  Hirotaka Yokoyama

IPC分类号： C01G49/00 ,  C04B35/26 ,  C09D5/23 ,  C09D7/12 ,  G11B5/706 ,  H01F1/11 ,  G11B5/70

CPC分类号： C04B35/2633 ,  G11B5/70678 ,  Y10T428/256 ,  Y10T428/257 ,  Y10T428/2978

摘要： A magnetic powder for magnetic recording media comprises a hexagonal crystalline system ferrite containing, as essential components for said hexagonal crystalline system ferrite, iron and oxygen, and at least one of the elements selected from the group of Ba, Sr, Ca and Pb, said iron being substituted by at least one of the elements selected from the group of Ti, Co, Ni, Mn, Cu, Zn, In, Ge, Nb, Zr and Sb; and at least one of Ba, Sr, Ca, Pb being substituted by at least one of the rare earth elements selected from the group of Ce, Pr, Nd, Pm, Sm and Eu. The magnetic powder has a mean particle size of 0.01 to 0.3 .mu.m and a coercive force of 200 and 2000 Oe. The magnetic powder is improved in its saturation magnetization while retaining a suitable coercive force. Accordingly, high reproduction output can be obtained in a magnetic recording medium employing the magnetic powder.

摘要翻译： 用于磁记录介质的磁性粉末包括六方晶系铁氧体，其包含作为所述六方晶系铁素体，铁和氧以及选自Ba，Sr，Ca和Pb中的至少一种元素的必要组分，所述六方晶系铁氧体包含所述六方晶系铁氧体， 铁被选自Ti，Co，Ni，Mn，Cu，Zn，In，Ge，Nb，Zr和Sb中的至少一种元素取代; 并且Ba，Sr，Ca，Pb中的至少一种被选自Ce，Pr，Nd，Pm，Sm和Eu中的至少一种稀土元素取代。 磁粉的平均粒径为0.01〜0.3μm，矫顽力为200〜2000Oe。 磁性粉末在保持适当的矫顽力的同时提高其饱和磁化强度。 因此，在使用磁性粉末的磁记录介质中可以获得高再现输出。