公开(公告)号：US09601500B2

公开(公告)日：2017-03-21

申请号：US14639063

申请日：2015-03-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

公开(公告)号：US20160379941A1

公开(公告)日：2016-12-29

申请号：US15258069

申请日：2016-09-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

IPC: H01L23/00 ,  H01L29/423 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

公开(公告)号：US09275748B2

公开(公告)日：2016-03-01

申请号：US14190010

申请日：2014-02-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Steven Malcolm Lemke ,  Jinho Kim ,  Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev

IPC: G11C16/26 ,  G11C16/14 ,  G11C16/04 ,  H01L21/28 ,  H01L29/788 ,  H01L27/115 ,  H01L29/423

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

Abstract: A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.

Abstract translation: 一种读取存储器件的方法，所述存储器件具有形成在衬底上的存储器单元的行和列，其中每个存储器单元包括间隔开的第一和第二区域，其间具有通道区域;布置在沟道区域的第一部分上的浮置栅极， 设置在通道区域的第二部分上的选择栅极，设置在浮置栅极上的控制栅极以及设置在第一区域上的擦除栅极。 该方法包括在读取操作期间在未选择的源极线上放置小的正电压和/或在未选择的字线上施加小的负电压以抑制亚阈值泄漏，从而提高读取性能。

公开(公告)号：US20140269062A1

公开(公告)日：2014-09-18

申请号：US14190010

申请日：2014-02-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Steven Malcolm Lemke ,  Jinho Kim ,  Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev

IPC: G11C16/26 ,  G11C16/14 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

Abstract: A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.

Abstract translation: 一种读取存储器件的方法，所述存储器件具有形成在衬底上的存储器单元的行和列，其中每个存储器单元包括间隔开的第一和第二区域，其间具有通道区域;布置在沟道区域的第一部分上的浮置栅极， 设置在通道区域的第二部分上的选择栅极，设置在浮置栅极上的控制栅极以及设置在第一区域上的擦除栅极。 该方法包括在读取操作期间在未选择的源极线上放置小的正电压和/或在未选择的字线上施加小的负电压以抑制亚阈值泄漏，从而提高读取性能。

公开(公告)号：US11362218B2

公开(公告)日：2022-06-14

申请号：US16910022

申请日：2020-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Elizabeth Cuevas ,  Yuri Tkachev ,  Parviz Ghazavi ,  Bernard Bertello ,  Gilles Festes ,  Bruno Villard ,  Catherine Decobert ,  Nhan Do ,  Jean Francois Thiery

IPC: H01L27/11517 ,  H01L27/11531 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11543 ,  H01L27/11551 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11534

Abstract: A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

公开(公告)号：US20210399127A1

公开(公告)日：2021-12-23

申请号：US16910022

申请日：2020-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Elizabeth Cuevas ,  Yuri Tkachev ,  Parviz Ghazavi ,  Bernard Bertello ,  Gilles Festes ,  Bruno Villard ,  Catherine Decobert ,  Nhan Do ,  Jean Francois Thiery

IPC: H01L29/788 ,  H01L29/66 ,  H01L27/11517

Abstract: A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

公开(公告)号：US20210193671A1

公开(公告)日：2021-06-24

申请号：US16724010

申请日：2019-12-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L27/11517 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/78

Abstract: A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

公开(公告)号：US10937794B2

公开(公告)日：2021-03-02

申请号：US16208150

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11521 ,  H01L21/28 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A memory device having plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin and a logic device formed on a second fin. The memory cell includes source and drain regions in the first fin with a channel region therebetween, a polysilicon floating gate extending along a first portion of the channel region including the side and top surfaces of the first fin, a metal select gate extending along a second portion of the channel region including the side and top surfaces of the first fin, a polysilicon control gate extending along the floating gate, and a polysilicon erase gate extending along the source region. The logic device includes source and drain regions in the second fin with a second channel region therebetween, and a metal logic gate extending along the second channel region including the side and top surfaces of the second fin.

公开(公告)号：US10727240B2

公开(公告)日：2020-07-28

申请号：US16028244

申请日：2018-07-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L27/1156 ,  H01L27/11524 ,  H01L21/266 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first of the fins, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second of the fins has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.

公开(公告)号：US10468428B1

公开(公告)日：2019-11-05

申请号：US15957615

申请日：2018-04-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.