公开(公告)号：US20050153487A1

公开(公告)日：2005-07-14

申请号：US11039602

申请日：2005-01-19

申请人： Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12 ,  H01L21/00

CPC分类号： H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

摘要： A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implanted-ion rich region in the Si-containing substrate. The implanted-ion rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

摘要翻译： 提供了使用SIMOX和Ge相互扩散形成基本上松弛的，优质的绝缘体上硅衬底材料的方法。 该方法包括首先将离子注入到含Si衬底中以在含Si衬底中形成植入离子富集区。 注入离子富集区具有足够的离子浓度，使得在随后的高温退火期间形成耐Ge扩散的阻挡层。 接下来，在含Si衬底的表面上形成Ge含有层，然后在允许形成阻挡层和Ge的相互扩散的温度下进行加热步骤，从而形成基本上松弛的单晶SiGe层 阻挡层顶部。

公开(公告)号：US20050056352A1

公开(公告)日：2005-03-17

申请号：US10662028

申请日：2003-09-12

申请人： Stephen Bedell ,  Kwang Choe ,  Keith Fogel ,  Devendra Sadana

发明人： Stephen Bedell ,  Kwang Choe ,  Keith Fogel ,  Devendra Sadana

IPC分类号： C22F1/10 ,  H01L21/20 ,  H01L21/762 ,  C22F1/00

CPC分类号： H01L21/76227 ,  C22F1/10 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/76245 ,  H01L29/78603

摘要： A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.

摘要翻译： 提供一种形成依赖于在含Ge层下形成的多孔硅层（或区域）的氧化的绝缘体上硅的简单且直接的方法。 该方法包括以下步骤：提供包括其中形成有富空穴的含Si衬底和含Si衬底顶部的含Ge层的结构; 将富含孔的区域转化为多孔区域; 并退火包括多孔区域的结构，以提供基本上松弛的绝缘体上的SiGe。

公开(公告)号：US07935612B1

公开(公告)日：2011-05-03

申请号：US12700801

申请日：2010-02-05

申请人： Stephen Bedell ,  Keith Fogel ,  Daniel Inns ,  Jeehwan Kim ,  Devendra Sadana ,  James Vichiconti

发明人： Stephen Bedell ,  Keith Fogel ,  Daniel Inns ,  Jeehwan Kim ,  Devendra Sadana ,  James Vichiconti

IPC分类号： H01L21/30 ,  H01L21/02

CPC分类号： H01L21/187

摘要： A method for layer transfer using a boron-doped silicon germanium (SiGe) layer includes forming a boron-doped SiGe layer on a bulk silicon substrate; forming an upper silicon (Si) layer over the boron-doped SiGe layer; hydrogenating the boron-doped SiGe layer; bonding the upper Si layer to an alternate substrate; and propagating a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate. A system for layer transfer using a boron-doped silicon germanium (SiGe) layer includes a bulk silicon substrate; a boron-doped SiGe layer formed on the bulk silicon substrate, such that the boron-doped SiGe layer is located underneath an upper silicon (Si) layer, wherein the boron-doped SiGe layer is configured to propagate a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate after hydrogenation of the boron-doped SiGe layer; and an alternate substrate bonded to the upper Si layer.

摘要翻译： 使用硼掺杂硅锗（SiGe）层进行层转移的方法包括在体硅衬底上形成硼掺杂的SiGe层; 在掺杂硼的SiGe层上形成上硅（Si）层; 氢化硼掺杂的SiGe层; 将上部Si层结合到替代的基底上; 并在硼掺杂的SiGe层和体硅衬底之间的界面处传播断裂。 使用硼掺杂硅锗（SiGe）层的层转移系统包括体硅衬底; 形成在本体硅衬底上的硼掺杂SiGe层，使得掺杂硼的SiGe层位于上硅（Si）层的下方，其中掺硼的SiGe层被配置为在 硼掺杂的SiGe层和硼硅掺杂SiGe层氢化后的体硅衬底; 以及与上部Si层接合的替代基板。

公开(公告)号：US20060003555A1

公开(公告)日：2006-01-05

申请号：US10883887

申请日：2004-07-02

申请人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  C30B1/00 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L21/76259 ,  Y10S438/967

摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

公开(公告)号：US20050095803A1

公开(公告)日：2005-05-05

申请号：US10984212

申请日：2004-11-09

申请人： Stephen Bedell ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Stephen Bedell ,  Keith Fogel ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

CPC分类号： H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

摘要： A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implant rich region in the Si-containing substrate. The implant rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

公开(公告)号：US20050082526A1

公开(公告)日：2005-04-21

申请号：US10685636

申请日：2003-10-15

申请人： Stephen Bedell ,  Keith Fogel ,  Bruce Furman ,  Sampath Purushothaman ,  Devendra Sadana ,  Anna Topol

发明人： Stephen Bedell ,  Keith Fogel ,  Bruce Furman ,  Sampath Purushothaman ,  Devendra Sadana ,  Anna Topol

IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L29/04

CPC分类号： H01L21/76259 ,  Y10T428/249961

摘要： Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein. In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a three dimensional integrated structure is provided.

摘要翻译： 提供了制造半导体器件的技术。 一方面，提供了层转移结构。 层转移结构包括具有调节孔隙度的多孔区域的载体衬底和在其中限定分离平面的注入物质的组合。 另一方面，提供了一种形成层转移结构的方法。 另一方面，提供一种形成三维一体化结构的方法。

公开(公告)号：US20050067055A1

公开(公告)日：2005-03-31

申请号：US10674647

申请日：2003-09-30

申请人： Kwang Choe ,  Keith Fogel ,  Siegfried Maurer ,  Ryan Mitchell ,  Devendra Sadana

发明人： Kwang Choe ,  Keith Fogel ,  Siegfried Maurer ,  Ryan Mitchell ,  Devendra Sadana

IPC分类号： H01L21/265 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/762 ,  C23C8/36

CPC分类号： H01L21/76243 ,  H01L21/26533 ,  H01L21/3063 ,  H01L21/31662

摘要： A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.

摘要翻译： 提供了一种制造在含Si的上层下方具有薄但均匀的掩埋氧化物区域的硅绝缘体（SOI）的方法。 通过首先修饰含Si衬底的表面以包含大量的空位或空隙的浓度来制造SOI结构。 接下来，含硅层通常但不总是形成在衬底顶上，然后使用低氧剂量将氧离子注入到结构中。 然后将结构退火以将注入的氧离子转化成薄但均匀的热掩埋氧化物区域。

公开(公告)号：US20060154429A1

公开(公告)日：2006-07-13

申请号：US11031142

申请日：2005-01-07

申请人： Joel de Souza ,  Keith Fogel ,  John Ott ,  Devendra Sadana ,  Katherine Saenger

发明人： Joel de Souza ,  Keith Fogel ,  John Ott ,  Devendra Sadana ,  Katherine Saenger

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/2022

摘要： The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.

摘要翻译： 本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向 具有不同的方向。 更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶 非晶层的原始方向。 本发明方法的关键组分是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以去除在初始再结晶退火之后残留的缺陷。 本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。

公开(公告)号：US20050148161A1

公开(公告)日：2005-07-07

申请号：US10751208

申请日：2004-01-02

申请人： Huajie Chen ,  Dan Mocuta ,  Richard Murphy ,  Stephan Bedell ,  Devendra Sadana

发明人： Huajie Chen ,  Dan Mocuta ,  Richard Murphy ,  Stephan Bedell ,  Devendra Sadana

IPC分类号： C30B25/02 ,  C30B29/06 ,  C30B29/52 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/36 ,  H01L21/44

CPC分类号： H01L21/02046 ,  C30B25/02 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02661 ,  Y10S438/933

摘要： The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves a first amount of oxygen (typically 1×1013-1×1015/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process which heats the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface sufficiently to remove additional oxygen from the surface and leave a second amount of oxygen, less than the first amount, on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The heating process leaves an amount of at least 5×1012/cm2 of oxygen (typically, between approximately 1×1013/cm2 and approximately 5×1013/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. By leaving a small amount of oxygen on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.

公开(公告)号：US20080057684A1

公开(公告)日：2008-03-06

申请号：US11873928

申请日：2007-10-17

申请人： Joel de Souza ,  Keith Fogel ,  John Ott ,  Devendra Sadana ,  Katherine Saenger

发明人： Joel de Souza ,  Keith Fogel ,  John Ott ,  Devendra Sadana ,  Katherine Saenger

IPC分类号： H01L21/425

CPC分类号： H01L21/26506 ,  H01L21/2022

摘要： The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.

摘要翻译： 本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向 具有不同的方向。 更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶 非晶层的原始方向。 本发明方法的关键组分是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以去除在初始再结晶退火之后残留的缺陷。 本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。