公开(公告)号：US20120009766A1

公开(公告)日：2012-01-12

申请号：US12830626

申请日：2010-07-06

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/20

CPC分类号： H01L29/1054 ,  H01L29/7833

摘要： A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer. After forming the relaxed and doped silicon layer on the SOI substrate, the dopant within the relaxed and doped silicon layer is removed from that layer converting the relaxed and doped silicon layer into a strained (compressively or tensilely) silicon layer that is formed on an upper surface of an SOI substrate.

摘要翻译： 提供了一种形成不包括晶片接合的应变绝缘体上半导体（SSOI）衬底的方法。 在本公开中，在绝缘体上硅（SOI）衬底的上表面上形成松弛和掺杂的硅层。 在一个实施例中，松弛和掺杂硅层内的掺杂剂具有小于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数小于硅的原子尺寸， 下层SOI层的平面晶格参数。 在另一实施例中，松弛和掺杂硅层内的掺杂剂具有大于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数大于硅原子尺寸， 下层SOI层的平面晶格参数。 在SOI衬底上形成松弛和掺杂的硅层之后，从该层去除松弛和掺杂硅层内的掺杂剂，将松散和掺杂的硅层转化成形成在上层的应变（压缩或拉伸）硅层 SOI衬底的表面。

公开(公告)号：US08039371B2

公开(公告)日：2011-10-18

申请号：US12496006

申请日：2009-07-01

申请人： Stephen W. Bedell ,  Jeehwan Kim ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Jeehwan Kim ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76283

摘要： A semiconductor-on-insulator hetero-structure and a method for fabricating the semiconductor -on-insulator hetero-structure include a crystalline substrate and a dielectric layer located thereupon having an aperture that exposes the crystalline substrate. The semiconductor-on -insulator hetero-structure and the method for fabricating the semiconductor-on-insulator hetero-structure also include a semiconductor layer of composition different than the crystalline substrate located within the aperture and upon the dielectric layer. A portion of the semiconductor layer located aligned over the aperture includes a defect. A portion of the semiconductor layer located aligned over the dielectric layer does not include a defect. Upon removing the portion of the semiconductor layer located aligned over the aperture a reduced defect semiconductor-on-insulator hetero-structure is formed.

摘要翻译： 绝缘体上半导体异质结构和制造半导体绝缘体异质结构的方法包括晶体衬底和位于其上的具有暴露结晶衬底的孔的电介质层。 半导体在 - 绝缘体异质结构和用于制造绝缘体上半导体异质结构的方法还包括组成不同于位于孔内和介电层上的晶体衬底的组成的半导体层。 定位在孔径上方的半导体层的一部分包括缺陷。 位于电介质层上的半导体层的一部分不包括缺陷。 在去除位于孔上对准的半导体层的部分之后，形成了缺陷半导体绝缘体上异质结构。

公开(公告)号：US20110001167A1

公开(公告)日：2011-01-06

申请号：US12496006

申请日：2009-07-01

申请人： Stephen W. Bedell ,  Jeehwan Kim ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Jeehwan Kim ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L29/267 ,  H01L29/165 ,  H01L29/161 ,  H01L21/20

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76283

摘要： A semiconductor-on-insulator hetero-structure and a method for fabricating the semiconductor-on-insulator hetero-structure include a crystalline substrate and a dielectric layer located thereupon having an aperture that exposes the crystalline substrate. The semiconductor-on-insulator hetero-structure and the method for fabricating the semiconductor-on-insulator hetero-structure also include a semiconductor layer of composition different than the crystalline substrate located within the aperture and upon the dielectric layer. A portion of the semiconductor layer located aligned over the aperture includes a defect. A portion of the semiconductor layer located aligned over the dielectric layer does not include a defect. Upon removing the portion of the semiconductor layer located aligned over the aperture a reduced defect semiconductor-on-insulator hetero-structure is formed.

摘要翻译： 绝缘体上半导体异质结构和制造绝缘体上半导体异质结构的方法包括晶体衬底和位于其上的具有曝光晶体衬底的孔的电介质层。 绝缘体上半导体异质结构和制造绝缘体上半导体异质结构的方法还包括组成不同于位于孔内和介电层上的晶体衬底的组成的半导体层。 定位在孔径上方的半导体层的一部分包括缺陷。 位于电介质层上的半导体层的一部分不包括缺陷。 在去除位于孔上对准的半导体层的部分之后，形成了缺陷半导体绝缘体上异质结构。

公开(公告)号：US07833884B2

公开(公告)日：2010-11-16

申请号：US11934479

申请日：2007-11-02

申请人： Stephen W. Bedell ,  Joel P. de Souza ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Joel P. de Souza ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L21/20

CPC分类号： H01L21/76245 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/3167

摘要： A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate is provided. The method includes first providing a structure that includes a substrate, a doped and relaxed semiconductor layer on the substrate, and a strained semiconductor layer on the doped and relaxed semiconductor layer. In the invention, the doped and relaxed semiconductor layer having a lower lattice parameter than the substrate. Next, at least the doped and relaxed semiconductor layer is converted into a buried porous layer and the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. During the annealing, the buried porous layer is converted into a buried oxide layer.

摘要翻译： 提供了制造应变半导体绝缘体（SSOI）衬底的方法。 该方法包括首先提供包括衬底，衬底上的掺杂和弛豫半导体层以及掺杂和弛豫半导体层上的应变半导体层的结构。 在本发明中，掺杂和松弛的半导体层具有比衬底更低的晶格参数。 接下来，至少将掺杂和松弛的半导体层转换成掩埋多孔层，并且将包括埋入多孔层的结构退火以提供应变绝缘体上半导体衬底。 在退火过程中，将埋入的多孔层转化为掩埋氧化物层。

公开(公告)号：US07172930B2

公开(公告)日：2007-02-06

申请号：US10883887

申请日：2004-07-02

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/36

CPC分类号： H01L21/76259 ,  Y10S438/967

摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

摘要翻译： 提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。 该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。 该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。 根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

公开(公告)号：US08809168B2

公开(公告)日：2014-08-19

申请号：US13037944

申请日：2011-03-01

申请人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L21/20 ,  H01L29/02

CPC分类号： H01L21/02381 ,  H01L21/02532 ,  H01L21/0262

摘要： Compressively strained silicon is epitaxially grown directly onto a silicon substrate at low temperature using hydrogen to engineer the strain level. Hydrogen dilution may be varied during such growth to provide a strain gradient.

摘要翻译： 使用氢将压缩应变硅在低温下直接外延生长到硅衬底上以设计应变水平。 在这样的生长过程中氢稀释可以变化以提供应变梯度。

公开(公告)号：US20130334571A1

公开(公告)日：2013-12-19

申请号：US13526840

申请日：2012-06-19

申请人： Alexander Reznicek ,  Thomas N. Adam ,  Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Alexander Reznicek ,  Thomas N. Adam ,  Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L29/78 ,  H01L29/24 ,  H01L21/20

CPC分类号： H01L29/165 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

摘要： A smooth germanium layer which can be grown directly on a silicon semiconductor substrate by exposing the substrate to germanium precursor in the presence of phosphine at temperature of about 350C. The germanium layer formation can be achieved with or without a SiGe seed layer. The process to form the germanium layer can be integrated into standard CMOS processing to efficiently form a structure embodying a thin, highly strained germanium layer. Such structure can enable processing flexibility. The germanium layer can also provide unique physical properties such as in an opto-electronic devices, or to enable formation of a layer of group III-V material on a silicon substrate.

摘要翻译： 可以在约350℃的温度下，在磷化氢存在下将衬底暴露于锗前体，可直接在硅半导体衬底上生长的光滑的锗层。 可以在有或没有SiGe种子层的情况下实现锗层形成。 形成锗层的过程可以集成到标准CMOS处理中，以有效地形成体现薄的，高度应变的锗层的结构。 这种结构可以实现处理灵活性。 锗层还可以提供独特的物理性质，例如在光电子器件中，或者能够在硅衬底上形成III-V族材料层。

公开(公告)号：US08415253B2

公开(公告)日：2013-04-09

申请号：US13075657

申请日：2011-03-30

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L21/311

CPC分类号： H01L21/02046

摘要： Low-temperature in-situ techniques are provided for the removal of oxide from a silicon surface during CMOS epitaxial processing. Oxide is removed from a semiconductor wafer having a silicon surface, by depositing a SiGe layer on the silicon surface; etching the SiGe layer from the silicon surface at a temperature below 700 C (and above, for example, approximately 450 C); and repeating the depositing and etching steps a number of times until a contaminant is substantially removed from the silicon surface. In one variation, the deposited layer comprises a group IV semiconductor material and/or an alloy thereof.

摘要翻译： 提供低温原位技术用于在CMOS外延处理期间从硅表面去除氧化物。 通过在硅表面上沉积SiGe层，从具有硅表面的半导体晶片去除氧化物; 在低于700℃（以上，例如约450℃）的温度下，从硅表面蚀刻SiGe层; 并重复沉积和蚀刻步骤多次，直到污染物基本上从硅表面除去。 在一个变型中，沉积层包括IV族半导体材料和/或其合金。

公开(公告)号：US08361889B2

公开(公告)日：2013-01-29

申请号：US12830626

申请日：2010-07-06

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/20

CPC分类号： H01L29/1054 ,  H01L29/7833

摘要： A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer. After forming the relaxed and doped silicon layer on the SOI substrate, the dopant within the relaxed and doped silicon layer is removed from that layer converting the relaxed and doped silicon layer into a strained (compressively or tensilely) silicon layer that is formed on an upper surface of an SOI substrate.

摘要翻译： 提供了一种形成不包括晶片接合的应变绝缘体上半导体（SSOI）衬底的方法。 在本公开中，在绝缘体上硅（SOI）衬底的上表面上形成松弛和掺杂的硅层。 在一个实施例中，松弛和掺杂硅层内的掺杂剂具有小于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数小于硅的原子尺寸， 下层SOI层的平面晶格参数。 在另一实施例中，松弛和掺杂硅层内的掺杂剂具有大于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数大于硅原子尺寸， 下层SOI层的平面晶格参数。 在SOI衬底上形成松弛和掺杂的硅层之后，从该层去除松弛和掺杂硅层内的掺杂剂，将松散和掺杂的硅层转化成形成在上层的应变（压缩或拉伸）硅层 SOI衬底的表面。

公开(公告)号：US20120112208A1

公开(公告)日：2012-05-10

申请号：US12942289

申请日：2010-11-09

申请人： THOMAS N. ADAM ,  Stephen W. Bedell ,  Abhishek Dube ,  Eric C.T. Harley ,  Judson R. Holt ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Matthew W. Stoker ,  Keith H. Tabakman

发明人： THOMAS N. ADAM ,  Stephen W. Bedell ,  Abhishek Dube ,  Eric C.T. Harley ,  Judson R. Holt ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Matthew W. Stoker ,  Keith H. Tabakman

IPC分类号： H01L29/772 ,  H01L29/24 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/28525 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.

摘要翻译： 在至少一个预制的场效应晶体管的覆盖区上形成嵌入的应变外延半导体材料，即嵌入的应力元件，该至少一个预制的场效应晶体管至少包括图案化的栅叠层，源极区和漏极区。 结果，保留嵌入的应变外延半导体材料的亚稳态，并且避免基于植入和退火的松弛机制，因为在形成嵌入的应变外延半导体材料之前执行注入和退火。