摘要:
A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
摘要:
A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
摘要:
A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
摘要:
A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
摘要:
A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.
摘要:
A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
摘要:
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
摘要:
A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
摘要:
A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
摘要:
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.