公开(公告)号：US08233210B2

公开(公告)日：2012-07-31

申请号：US12319014

申请日：2008-12-30

Applicant: Charles Wallace ,  Matthew Tingey ,  Swaminathan Sivakumar

Inventor： Charles Wallace ,  Matthew Tingey ,  Swaminathan Sivakumar

IPC: G02B26/02 ,  G03B27/54 ,  G03B27/72

CPC classification number: G03B27/72 ,  G03F7/701 ,  G03F7/70191

Abstract: Embodiments of systems and methods for providing a hybrid illumination aperture in optical lithography are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文中通常描述用于在光学光刻中提供混合照明孔径的系统和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US07927959B2

公开(公告)日：2011-04-19

申请号：US12286338

申请日：2008-09-30

Applicant: Steven J. Keating ,  Nick Lindert ,  Nadia Rahhal-Orabi ,  Brian Doyle ,  Satyarth Suri ,  Swaminathan Sivakumar ,  Lana Jong ,  Lin Sha

Inventor： Steven J. Keating ,  Nick Lindert ,  Nadia Rahhal-Orabi ,  Brian Doyle ,  Satyarth Suri ,  Swaminathan Sivakumar ,  Lana Jong ,  Lin Sha

IPC: H01L21/467

CPC classification number: H01L28/40 ,  H01G4/012 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract translation: 在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分 （435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料 湿蚀刻化学。 所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。

公开(公告)号：US20100062228A1

公开(公告)日：2010-03-11

申请号：US12205744

申请日：2008-09-05

Applicant: Paul Nyhus ,  Charles Wallace ,  Swaminathan Sivakumar

Inventor： Paul Nyhus ,  Charles Wallace ,  Swaminathan Sivakumar

IPC: G03F7/20 ,  B32B5/00

CPC classification number: G03F7/0035 ,  Y10T428/24802

Abstract: A method of forming a pattern on a wafer is provided. The method includes applying a photoresist on the wafer and exposing the wafer to define a first pattern on the photoresist. The method also includes exposing the wafer to define a second pattern on the photoresist, wherein each of the first and second patterns comprises unexposed portions of the photoresist and developing the wafer to form the first and second patterns on the photoresist, wherein the first and second patterns are formed by removing the unexposed portions of the photoresist.

Abstract translation: 提供了在晶片上形成图案的方法。 该方法包括在晶片上施加光致抗蚀剂并暴露晶片以在光致抗蚀剂上限定第一图案。 该方法还包括曝光晶片以限定光致抗蚀剂上的第二图案，其中第一和第二图案中的每一个包括光致抗蚀剂的未曝光部分，并且显影晶片以在光致抗蚀剂上形成第一和第二图案，其中第一和第二图案 通过去除光致抗蚀剂的未曝光部分形成图案。

公开(公告)号：US20090263751A1

公开(公告)日：2009-10-22

申请号：US12148826

申请日：2008-04-22

Applicant: Swaminathan Sivakumar ,  Anna Lio ,  Elliot Tan ,  Charles Wallace ,  Anant Jahagirdar

Inventor： Swaminathan Sivakumar ,  Anna Lio ,  Elliot Tan ,  Charles Wallace ,  Anant Jahagirdar

IPC: G03F7/38

CPC classification number: G03F7/38 ,  G03F7/405 ,  H01L21/0274

Abstract: Embodiments of methods for double patterning photoresist are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述用于双重图案化光刻胶的方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20080318137A1

公开(公告)日：2008-12-25

申请号：US11820420

申请日：2007-06-19

Applicant: Richard Schenker ,  Swaminathan Sivakumar ,  Paul Nyhus ,  Sven Henrichs

Inventor： Richard Schenker ,  Swaminathan Sivakumar ,  Paul Nyhus ,  Sven Henrichs

IPC: G03F1/00

CPC classification number: G03F1/34 ,  G03F1/32 ,  G03F1/36

Abstract: In one embodiment, a mask for use in semiconductor processing comprises a first region formed from a first material that is primarily opaque, a second region formed from a second material that is primarily transmissive, and a third region in which at least a portion of the second material is removed to generate a phase shift in radiation applied to the mask.

Abstract translation: 在一个实施例中，用于半导体处理的掩模包括由主要是不透明的第一材料形成的第一区域，由主要透射的第二材料形成的第二区域，以及第三区域，其中至少一部分 第二材料被去除以产生施加到掩模的辐射的相移。

公开(公告)号：US07358111B2

公开(公告)日：2008-04-15

申请号：US11262247

申请日：2005-10-28

Applicant: Swaminathan Sivakumar

Inventor： Swaminathan Sivakumar

IPC: H01L21/00

CPC classification number: G03F7/095 ,  G03F7/091 ,  H01L21/0276

Abstract: A semiconductor wafer may be coated with an imageable anti-reflective coating. As a result, the coating may be removed using the same techniques used to remove overlying photoresists. This may overcome the difficulty of etching anti-reflective coatings using standard etches because of their poor selectivity to photoresist and the resulting propensity to cause integrated circuit defects arising from anti-reflective coating remnants.

Abstract translation: 可以用可成像的抗反射涂层涂覆半导体晶片。 结果，可以使用用于去除覆盖的光致抗蚀剂的相同技术去除涂层。 这可以克服使用标准蚀刻来蚀刻抗反射涂层的难度，因为它们对光致抗蚀剂的选择性差，并导致由抗反射涂层残留物引起集成电路缺陷的倾向。

公开(公告)号：US06977219B2

公开(公告)日：2005-12-20

申请号：US10749739

申请日：2003-12-30

Applicant: Rex K. Frost ,  Swaminathan Sivakumar

Inventor： Rex K. Frost ,  Swaminathan Sivakumar

IPC: G03F7/40 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768

CPC classification number: G03F7/40 ,  H01L21/0273 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76802

Abstract: The present invention relates to the reduction of critical dimensions and the reduction of feature sizes in manufacturing integrated circuits. Specifically, the method controls photoresist flow rates to develop critical dimensions beyond the resolution limits of the photoresist material used, and the limits of lithographic tool sets. The post exposure and developed resist pattern is exposed to a solvent prior to a bake or reflow process. Exposure to the solvent lowers the molecular weight of the resist material, modifying the resist material's reflow rate. The post-exposure resist is then easier to control during a subsequent reflow process to reduce the hole or line size of the patterned resist.

Abstract translation: 本发明涉及减小制造集成电路中的关键尺寸和减小特征尺寸。 具体地说，该方法控制光致抗蚀剂的流速，以发展超出所使用的光致抗蚀剂材料的分辨率极限以及光刻工具组的极限的关键尺寸。 在烘烤或回流处理之前，将后曝光和显影的抗蚀剂图案暴露于溶剂。 暴露于溶剂会降低抗蚀剂材料的分子量，改变抗蚀材料的回流速率。 在后续回流过程中，后曝光抗蚀剂更容易控制，以减小图案化抗蚀剂的孔或线尺寸。

公开(公告)号：US20050097502A1

公开(公告)日：2005-05-05

申请号：US10698782

申请日：2003-10-31

Applicant: Rex Frost ,  Swaminathan Sivakumar

Inventor： Rex Frost ,  Swaminathan Sivakumar

IPC: G03F1/14 ,  G06F17/50 ,  G03F9/00

CPC classification number: G03F1/36

Abstract: Systems and techniques for accommodating diffraction in the printing of features on a substrate. In one implementation, a method includes identifying a pair of features to be printed using a corresponding pair of patterning elements and increasing a separation distance between the pair of patterning elements while maintaining the sufficiently small pitch between the corresponding imaged features. The pitch of the pair of features can be sufficiently small that, upon printing, diffraction will make a separation between the features smaller than a separation between the corresponding pair of patterning elements.

Abstract translation: 用于在基板上的特征的印刷中适应衍射的系统和技术。 在一个实现中，一种方法包括使用相应的一对图案化元件识别要打印的特征对，并且增加一对图案化元件之间的间隔距离，同时保持相应的成像特征之间足够小的间距。 一对特征的间距可以足够小，使得在印刷时，衍射将使特征之间的间隔小于相应的一对构图元件之间的间隔。

公开(公告)号：US09716037B2

公开(公告)日：2017-07-25

申请号：US13995678

申请日：2011-12-22

Applicant: Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

Inventor： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

IPC: H01L21/768 ,  H01L27/088 ,  H01L21/306 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28008 ,  H01L21/30625 ,  H01L21/32 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

公开(公告)号：US20150348839A1

公开(公告)日：2015-12-03

申请号：US14822865

申请日：2015-08-10

Applicant: Paul A. Nyhus ,  Swaminathan Sivakumar ,  Robert Bristol

Inventor： Paul A. Nyhus ,  Swaminathan Sivakumar ,  Robert Bristol

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

CPC classification number: H01L21/76877 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.

Abstract translation: 一方面的方法包括在硬掩模层中形成互连线蚀刻开口。 硬掩模层位于其中布置有互连线的电介质层上。 互连线蚀刻开口在互连线上形成对准。 将嵌段共聚物引入到互连线蚀刻开口中。 嵌段共聚物被组装以形成沿着互连线蚀刻开口的长度间隔开的多个组装结构。 组装的结构在设置在电介质层内的互连线上直接对准。