公开(公告)号：US11508585B2

公开(公告)日：2022-11-22

申请号：US16902180

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Liang-Guang Chen ,  Kei-Wei Chen ,  Hung Yen ,  Ting-Hsun Chang ,  Chi-Hsiang Shen ,  Li-Chieh Wu ,  Chi-Jen Liu

IPC: H01L21/321 ,  C09G1/02 ,  B24B37/10 ,  B24B37/04

Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.

公开(公告)号：US11211289B2

公开(公告)日：2021-12-28

申请号：US16556360

申请日：2019-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/3115 ,  H01L23/532

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US10916473B2

公开(公告)日：2021-02-09

申请号：US16655509

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/535 ,  H01L21/285 ,  H01L23/485

Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

公开(公告)号：US10515808B2

公开(公告)日：2019-12-24

申请号：US15267670

申请日：2016-09-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Chi-Jen Liu ,  Ying-Liang Chuang ,  Li-Chieh Wu ,  Liang-Guang Chen ,  Ming-Liang Yen

IPC: H01L21/28 ,  H01L21/321 ,  H01L21/02 ,  H01L29/66 ,  B24B37/20 ,  H01L21/67

Abstract: A chemical mechanical polishing (CMP) system includes an O3/DIW generator, a polishing unit, and a cleaning unit. The O3/DIW generator is configured to generate an O3/DIW solution including ozone gas (O3) dissolved in deionized water (DIW). The polishing unit includes components for buffing a surface of a semiconductor structure, and a pipeline coupled to the O3/DIW generator to receive the O3/DIW solution for the buffing. The cleaning unit is coupled to the O3/DIW generator and is configured to clean the surface of the semiconductor structure using the O3/DIW solution.

公开(公告)号：US20190385909A1

公开(公告)日：2019-12-19

申请号：US16556360

申请日：2019-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US10510594B2

公开(公告)日：2019-12-17

申请号：US16050168

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/02 ,  H01L21/285 ,  H01L23/485

Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

公开(公告)号：US09917173B2

公开(公告)日：2018-03-13

申请号：US15407784

申请日：2017-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, LTD.

Inventor： Chi-Jen Liu ,  Li-Chieh Wu ,  Liang-Guang Chen ,  Shich-Chang Suen

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76895 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen.

公开(公告)号：US12297375B2

公开(公告)日：2025-05-13

申请号：US17141988

申请日：2021-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ji Cui ,  Chi-Jen Liu ,  Liang-Guang Chen ,  Kei-Wei Chen ,  Chun-Wei Hsu ,  Li-Chieh Wu ,  Peng-Chung Jangjian ,  Kao-Feng Liao ,  Fu-Ming Huang ,  Wei-Wei Liang ,  Tang-Kuei Chang ,  Hui-Chi Huang

IPC: C09G1/02 ,  H01L21/321 ,  H01L21/768 ,  H01L23/535

Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.

公开(公告)号：US20250038008A1

公开(公告)日：2025-01-30

申请号：US18360930

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Hsiang Cheng ,  Ting-Kui Chang ,  Fu-Ming Huang ,  Li-Chieh Wu ,  Che-Hao Tu

IPC: H01L21/321 ,  C09G1/02 ,  H01L21/768

Abstract: Methods for chemical mechanical polishing (CMP), and methods for forming an interconnect structure of a semiconductor device are provided. The methods include performing CMP on a surface of a dielectric structure with a CMP slurry to remove a portion of a metal layer formed in the dielectric structure and having at least a first layer exposed through the surface. In some examples, the CMP slurry that includes an abrasive, an oxidizing agent, and a compound configured to reduce aggregation of the abrasive on the surface of the dielectric structure. In some examples, the compound has positively charged ions that interact with the abrasive to reduce aggregation of the abrasive on a dielectric material. In some examples, the CMP slurry includes potassium hydroxide. In some examples, the compound includes an ammonium salt.

公开(公告)号：US12002684B2

公开(公告)日：2024-06-04

申请号：US18057728

申请日：2022-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Liang-Guang Chen ,  Kei-Wei Chen ,  Hung Yen ,  Ting-Hsun Chang ,  Chi-Hsiang Shen ,  Li-Chieh Wu ,  Chi-Jen Liu

IPC: H01L21/321 ,  B24B37/04 ,  B24B37/10 ,  C09G1/02

CPC classification number: H01L21/3212 ,  B24B37/044 ,  B24B37/107 ,  C09G1/02

Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.