中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

63 records (took 0.023 seconds)

    Semiconductor processing tool and methods of operation
    1.
    发明授权
    Semiconductor processing tool and methods of operation 有权

    公开(公告)号：US12068169B2

    公开(公告)日：2024-08-20

    申请号：US17446248

    申请日：2021-08-27

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ji Cui ,  Chih Hung Chen ,  Liang-Guang Chen ,  Kei-Wei Chen

    IPC: H01L21/321 ,  H01L21/67 ,  H01L21/768

    CPC classification number: H01L21/3212 ,  H01L21/67046 ,  H01L21/67051 ,  H01L21/76814

    Abstract: A semiconductor processing tool includes a cleaning chamber configured to perform a post-chemical mechanical polishing/planarization (post-CMP) cleaning operation in an oxygen-free (or in a near oxygen-free) manner. An inert gas may be provided into the cleaning chamber to remove oxygen from the cleaning chamber such that the post-CMP cleaning operation may be performed in an oxygen-free (or in a near oxygen-free) environment. In this way, the post-CMP cleaning operation may be performed in an environment that may reduce oxygen-causing corrosion of metallization layers and/or metallization structures on and/or in the semiconductor wafer, which may increase semiconductor processing yield, may decrease semiconductor processing defects, and/or may increase semiconductor processing quality, among other examples.

    FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME
    3.
    发明申请
    FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开

    公开(公告)号：US20190103312A1

    公开(公告)日：2019-04-04

    申请号：US16104006

    申请日：2018-08-16

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Shich-Chang Suen ,  Kei-Wei Chen ,  Liang-Guang Chen

    IPC: H01L21/768 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L21/033 ,  H01L29/78 ,  H01L23/522

    Abstract: A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.

Patent Agency Ranking