公开(公告)号：US09691751B2

公开(公告)日：2017-06-27

申请号：US14570530

申请日：2014-12-15

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Khanh Quang Le ,  Collin White ,  Sopa Chevacharoenkul ,  Ashley Norris ,  Bernard John Fischer

IPC: H01L27/02 ,  H01L21/763 ,  H01L29/06

CPC classification number: H01L27/0248 ,  H01L21/763 ,  H01L21/823878 ,  H01L29/0649

Abstract: A method of fabricating an integrated circuit (IC) includes etching a trench in a semiconductor substrate having an aspect ratio (AR) ≧5 and a trench depth ≧10 μm. A dielectric liner is formed along the walls of the trench to form a dielectric lined trench. In-situ doped polysilicon is deposited into the trench to form a dielectric lined polysilicon filled trench having a doped polysilicon filler therein. The doped polysilicon filler after completion of fabricating the IC is essentially polysilicon void-free and has a 25° C. sheet resistance ≦100 ohms/sq. The method can include etching an opening at a bottom of the dielectric liner before depositing the polysilicon to provide ohmic contact to the semiconductor substrate.

公开(公告)号：US12170310B2

公开(公告)日：2024-12-17

申请号：US16453796

申请日：2019-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Guruvayurappan S. Mathur ,  Abbas Ali ,  Poornika Fernandes ,  Bhaskar Srinivasan ,  Darrell R. Krumme ,  Joao Sergio Afonso ,  Shih-Chang Chang ,  Shariq Arshad

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/06 ,  H01L49/02

Abstract: In some examples, an integrated circuit includes an isolation layer disposed on or over a semiconductor substrate. The integrated circuit also includes a first conductive plate located over the isolation layer and a composite dielectric layer located over the first conductive plate. The composite dielectric layer includes a first sublayer comprising a first chemical composition; a second sublayer comprising a second different chemical composition; and a third sublayer comprising a third chemical composition substantially similar to the first chemical composition. The integrated circuit further includes a second conductive plate located directly on the composite dielectric layer above the first conductive plate.

公开(公告)号：US20240290785A1

公开(公告)日：2024-08-29

申请号：US18176430

申请日：2023-02-28

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Bhaskar Srinivasan ,  John Shriner ,  Edmond B. Benton

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431

Abstract: Forming an integrated circuit by first, forming a first fin and a second fin from a semiconductor layer, with an area between the first fin and the second fin, second, forming a dielectric layer covering at least a portion of the first fin, at least a portion of the second fin, and at least a portion of the area, and third, forming amorphous polysilicon covering a least a portion of the dielectric layer.

公开(公告)号：US11849590B2

公开(公告)日：2023-12-19

申请号：US17479542

申请日：2021-09-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Carl Sebastian Morandi ,  Susan Trolier-McKinstry ,  Kezhakkedath Ramunni Udayakumar ,  John Anthony Rodriguez ,  Bhaskar Srinivasan

IPC: H01L27/11507 ,  H10B53/30 ,  H01L49/02

CPC classification number: H10B53/30 ,  H01L28/55 ,  H01L28/56 ,  H01L28/57

Abstract: In some examples, a system comprises a capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and the second plates and comprising a Bismuth Metal Oxide-Based Lead Titanate thin film. The capacitor further comprises a dielectric layer disposed on a transistor, wherein the capacitor is disposed on the dielectric layer.

公开(公告)号：US20230245891A1

公开(公告)日：2023-08-03

申请号：US17589329

申请日：2022-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bhaskar Srinivasan ,  Pushpa Mahalingam ,  Mahalingam Nandakumar ,  Mona Eissa ,  Corinne Gagnet ,  Christopher Whitesell

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8234

CPC classification number: H01L21/28052 ,  H01L27/088 ,  H01L29/4933 ,  H01L21/823443

Abstract: A system and method for growing fine grain polysilicon. In one example, the method of forming an integrated circuit includes forming a dielectric layer over a semiconductor substrate, and forming a polysilicon layer over the dielectric layer. The polysilicon layer is formed by a chemical vapor deposition process that includes providing a gas flow including disilane and hydrogen gas over the semiconductor substrate.

公开(公告)号：US20230178372A1

公开(公告)日：2023-06-08

申请号：US17545209

申请日：2021-12-08

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Walter Scott Idol ,  Ming-Yeh Chuang ,  Brian Goodlin

IPC: H01L21/225 ,  H01L29/66

CPC classification number: H01L21/2251 ,  H01L29/66681 ,  H01L29/66795

Abstract: A fin field-effect transistor (“FinFET”) semiconductor device and method of forming the same. In one example, a semiconductor fin is formed over a semiconductor substrate. A conformal dielectric layer is formed on a top and side surfaces of the fin. A doped semiconductor layer is formed over the conformal dielectric layer, the doped semiconductor layer including a dopant. The doped semiconductor layer is heated thereby driving the dopant through the conformal dielectric layer and forming a doped region of the fin.

公开(公告)号：US11616011B2

公开(公告)日：2023-03-28

申请号：US17360183

申请日：2021-06-28

Applicant: Texas Instruments Incorporated

Inventor： Mona M. Eissa ,  Umamaheswari Aghoram ,  Pushpa Mahalingam ,  Erich Wesley Kinder ,  Bhaskar Srinivasan ,  Brian E. Goodlin

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over the filled trench. A filled via through the second ILD layer provides a connection to the top capacitor plate.

公开(公告)号：US11171200B2

公开(公告)日：2021-11-09

申请号：US16584463

申请日：2019-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  David Matthew Curran ,  Stephen Arion Meisner ,  Bhaskar Srinivasan ,  Guruvayurappan S. Mathur ,  Scott William Jessen ,  Shih Chang Chang ,  Russell Duane Fields ,  Thomas Terrance Lynch

IPC: H01L49/02 ,  H01L21/02

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US20210074630A1

公开(公告)日：2021-03-11

申请号：US16564849

申请日：2019-09-09

Applicant: Texas Instruments Incorporated

Inventor： Mona M. Eissa ,  Umamaheswari Aghoram ,  Pushpa Mahalingam ,  Erich Wesley Kinder ,  Bhaskar Srinivasan ,  Brian E. Goodlin

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over including the filled trench. A filled via through the second ILD layer provides a contact to a top plate contact on the top capacitor plate.

公开(公告)号：US10157915B1

公开(公告)日：2018-12-18

申请号：US15793607

申请日：2017-10-25

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Shih Chang Chang ,  Poornika Gayathri Fernandes ,  Haowen Bu ,  Guru Mathur

IPC: H01L27/08 ,  H01L49/02 ,  H01L27/06 ,  H01L27/108 ,  H01L29/66 ,  H01L21/02 ,  H01L21/82

Abstract: A microelectronic device includes a capacitor having a lower plate of interconnect metal, a capacitor dielectric layer with a lower silicon dioxide layer, a silicon oxy-nitride layer, and an upper silicon dioxide layer, and an upper plate over the upper silicon dioxide layer. The silicon oxy-nitride layer has an average index of refraction of 1.60 to 1.75 at a wavelength of 248 nanometers. To form the microelectronic device, the lower silicon dioxide layer, the silicon oxy-nitride layer, and the upper silicon dioxide layer are formed in sequence over an interconnect metal layer. An upper plate layer is patterned to form the upper plate, leaving the lower silicon dioxide layer and at least half of the silicon oxy-nitride layer over the interconnect metal layer. An interconnect mask is formed of photoresist over the upper plate and the silicon oxy-nitride layer, using the silicon oxy-nitride layer as an anti-reflection layer.