公开(公告)号：US20150377964A1

公开(公告)日：2015-12-31

申请号：US14755728

申请日：2015-06-30

Applicant: Texas Instruments Incorporated

Inventor： Raja Reddy PATUKURI ,  Jagannathan Venkataraman

IPC: G01R31/3187 ,  G01S17/02 ,  H04N17/00

CPC classification number: G01S17/02 ,  G01S7/4863 ,  G01S7/497 ,  H04N17/002

Abstract: The disclosure provides a circuit capable of generating programmable test patterns for a pixel array. The circuit includes a pixel array having a plurality of pixels arranged in a plurality of rows and a plurality of columns. A built-in-tester is coupled to the pixel array. The built-in-tester includes a data pattern register that generates a plurality of test patterns. A switching logic circuit is coupled between the data pattern register and the pixel array. The switching logic circuit provides to each column of the plurality of columns one of a first voltage and a second voltage based on a test pattern of the plurality of test patterns received from the data pattern register.

Abstract translation: 本公开提供了一种能够产生像素阵列的可编程测试图案的电路。 电路包括具有以多行排列的多个像素和多列的像素阵列。 内置测试仪耦合到像素阵列。 内置测试器包括产生多个测试图案的数据模式寄存器。 开关逻辑电路耦合在数据模式寄存器和像素阵列之间。 基于从数据模式寄存器接收的多个测试模式的测试模式，开关逻辑电路向多列的每列提供第一电压和第二电压之一。

公开(公告)号：US20150260571A1

公开(公告)日：2015-09-17

申请号：US14644308

申请日：2015-03-11

Applicant: Texas Instruments Incorporated

Inventor： Jagannathan Venkataraman ,  Prabu Sankar Thirugnanam ,  Raja Reddy Patukuri ,  Sandeep Kesrimal Oswal

IPC: G01J1/44 ,  H03M3/00 ,  H01L27/144

CPC classification number: H03M3/30 ,  H03M3/402 ,  H03M3/43 ,  H03M3/494

Abstract: The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.

Abstract translation: 本公开提供了具有高动态范围的接收机。 接收器包括产生电流信号的光电二极管。 耦合电容器耦合到光电二极管，并且响应于从光电二极管接收的电流信号而产生调制信号。 Σ-Δ模数转换器（ADC）耦合到耦合电容器，并且响应于调制信号产生数字数据。 数字混频器耦合到Σ-ΔADC，并产生对应于数字数据的同相分量和正交分量。 处理器耦合到数字混频器，并处理与数字数据相对应的同相分量和正交分量。

公开(公告)号：US12244319B2

公开(公告)日：2025-03-04

申请号：US17977834

申请日：2022-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthikeyan Gunasekaran ,  Jagannathan Venkataraman

IPC: H03L7/089 ,  H03L7/099

Abstract: In an example, a system includes a phase frequency detector (PFD) coupled to a charge pump, and a loop filter coupled to the charge pump. The system also includes a voltage controlled oscillator (VCO) coupled to the loop filter. The system includes a fast Fourier transform (FFT) engine coupled to an output of the VCO, the FFT engine configured to estimate a phase and a magnitude of reference spurs of an input reference signal. The system includes spur correction circuitry coupled to an input of the VCO, the spur correction circuitry configured to correct for the reference spurs of the input reference signal based at least in part on the phase and magnitude of the reference spurs.

公开(公告)号：US11469928B2

公开(公告)日：2022-10-11

申请号：US17363855

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Ani Xavier ,  Jagannathan Venkataraman ,  Nagalinga Swamy Basayya Aremallapur ,  Aviral Singhal ,  Arun Mohan ,  Rakesh Chikkanayakanahalli Manjunath ,  Aravind Ganesan ,  Harshavardhan Adepu

IPC: H04L25/06 ,  H04L25/03 ,  H04L25/02

Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

公开(公告)号：US20220247420A1

公开(公告)日：2022-08-04

申请号：US17467561

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Eeshan Miglani ,  Chirag Chandrahas Shetty ,  Neeraj Shrivastava ,  Shagun Dusad ,  Srinivas Kumar Reddy Naru ,  Nithin Gopinath ,  Charls Babu ,  Shivam Srivastava ,  Viswanathan Nagarajan ,  Jagannathan Venkataraman ,  Harshit Moondra ,  Prasanth K ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

公开(公告)号：US11316525B1

公开(公告)日：2022-04-26

申请号：US17158526

申请日：2021-01-26

Applicant: Texas Instruments Incorporated

Inventor： Visvesvaraya Appala Pentakota ,  Narasimhan Rajagopal ,  Chirag Chandrahas Shetty ,  Prasanth K ,  Neeraj Shrivastava ,  Eeshan Miglani ,  Jagannathan Venkataraman

IPC: H03M1/10 ,  H03M1/66 ,  H03M1/12

Abstract: An analog-to-digital converter system includes a digital-to-analog converter for generating calibration voltages based on digital input codes, and an analog-to-digital converter, connected to the digital-to-analog converter, for receiving the calibration voltages from the digital-to-analog converter, for receiving sampled voltages, for generating digital output codes based on the calibration voltages, and for generating digital output codes based on the sampled voltages. The analog-to-digital converter system may have a lookup table, connected to the analog-to-digital converter, for storing the first digital output codes in association with the digital input codes. A method of calibrating an analog-to-digital converter system is also disclosed.

公开(公告)号：US11233525B2

公开(公告)日：2022-01-25

申请号：US16748849

申请日：2020-01-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagannathan Venkataraman ,  Prabu Sankar Thirugnanam ,  Raja Reddy Patukuri ,  Sandeep Kesrimal Oswal

IPC: H03M3/00

Abstract: The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.

公开(公告)号：US11063623B2

公开(公告)日：2021-07-13

申请号：US16692006

申请日：2019-11-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara Gunturi ,  Chandrasekhar Sriram ,  Jawaharlal Tangudu ,  Eeshan Miglani ,  Jagannathan Venkataraman

IPC: H04B1/30 ,  H04B1/10

Abstract: A non-linearity correction module, an optional droop corrector, and a zero-IF receiver with the non-linearity correction module and an optional droop corrector, wherein the non-linearity correction module is configured to generate a non-linearity term scaled to mitigate an inter-modulation component term of a RF signal received by the zero-IF receiver based on a test signal to enhance linearity in the zero-IF receiver and the optional droop corrector is configured to compensate a droop within a signal band of interest, caused by an analog low pass filter filtering a RF signal received by the zero-IF receiver, before a down-converted RF signal is fed into the non-linearity module.

公开(公告)号：US10425044B1

公开(公告)日：2019-09-24

申请号：US16192048

申请日：2018-11-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagannathan Venkataraman ,  Eeshan Miglani ,  Karthikeyan Gunasekaran

IPC: H03F1/32 ,  H03F1/30 ,  H03F1/18 ,  H03F5/00

Abstract: A circuit includes first and second operational amplifiers, each including positive and negative inputs and first and second internal nodes. A mixer couples first and second input nodes to the positive and negative inputs of the operational amplifiers. The mixer switches the first and second input nodes between the positive and negative inputs of the first and second operational amplifiers in accordance with clock signals. A first cancellation capacitor couples to the first input node, and a second cancellation capacitor couple to the second input node. First and second switches selectively couple the first cancellation capacitor to the first and second internal nodes, respectively, of the first operational amplifier. Third and fourth switches selectively couple the second cancellation capacitor to the first and second internal nodes, respectively, of the second operational amplifier.

公开(公告)号：US10111624B2

公开(公告)日：2018-10-30

申请号：US15936029

申请日：2018-03-26

Applicant: Texas Instruments Incorporated

Inventor： Anand Hariraj Udupa ,  Jagannathan Venkataraman ,  Hussam Ahmed ,  Sandeep Kesrimal Oswal

IPC: A61B5/00 ,  A61B5/053

Abstract: The disclosure provides a circuit for impedance measurement. The circuit includes an excitation source coupled between a first set of input switches. An impedance network is coupled between the first set of input switches and a first set of output switches. The impedance network includes a body impedance and a plurality of electrode impedances. A sense circuit is coupled to the first set of output switches. The sense circuit measures the body impedance and at least one electrode impedance of the plurality of electrode impedances.