公开(公告)号：US12211800B2

公开(公告)日：2025-01-28

申请号：US17500086

申请日：2021-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Liang Wan ,  Makarand Ramkrishna Kulkarni ,  Jie Chen ,  Steven Alfred Kummerl

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

公开(公告)号：US20240304517A1

公开(公告)日：2024-09-12

申请号：US18180024

申请日：2023-03-07

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Jie Chen ,  Yutaka Suzuki ,  Rajen Murugan

IPC: H01L23/373 ,  H01L21/56 ,  H01L21/784 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/3737 ,  H01L21/565 ,  H01L21/784 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/165 ,  H01L2224/08235 ,  H01L2224/273 ,  H01L2224/29193 ,  H01L2224/32221 ,  H01L2224/94 ,  H01L2924/182

Abstract: An electronic device includes: a semiconductor die having opposite first and second sides and a conductive terminal along the first side; a conductive lead electrically coupled to the conductive terminal; a package structure that forms a top side of the electronic device and encloses a portion of the semiconductor die, the package structure including a first molding compound having a first thermal conductivity; and a thermally conductive layer on at least a portion of the second side of the semiconductor die, the thermally conductive layer including a second molding compound having a second thermal conductivity that is greater than the first thermal conductivity.

公开(公告)号：US11621232B2

公开(公告)日：2023-04-04

申请号：US17246115

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Jie Chen ,  Yiqi Tang ,  Rajen Murugan ,  Liang Wan

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

公开(公告)号：US20220352087A1

公开(公告)日：2022-11-03

申请号：US17246115

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Jie Chen ,  Yiqi Tang ,  Rajen Murugan ,  Liang Wan

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

公开(公告)号：US20210159403A1

公开(公告)日：2021-05-27

申请号：US17142539

申请日：2021-01-06

Applicant: Texas Instruments Incorporated

Inventor： Ming Li ,  Yiqi Tang ,  Jie Chen ,  Enis Tuncer ,  Usman Mahmood Chaudhry ,  Tony Ray Larson ,  Rajen Manicon Murugan ,  John Paul Tellkamp ,  Satyendra Singh Chauhan

IPC: H01L43/14 ,  H01L43/06 ,  G01R15/20 ,  H01L23/495 ,  G01R33/07

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

公开(公告)号：US09941228B2

公开(公告)日：2018-04-10

申请号：US15497024

申请日：2017-04-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajen Manicon Murugan ,  Minhong Mi ,  Gary Paul Morrison ,  Jie Chen ,  Kenneth Robert Rhyner ,  Stanley Craig Beddingfield ,  Chittranjan Mohan Gupta ,  Django Earl Trombley

IPC: H01Q1/00 ,  H01L23/66 ,  H01L23/498 ,  H01L23/00 ,  H05K1/18 ,  H05K1/02 ,  H01Q1/22 ,  H01Q1/32 ,  H01Q23/00

CPC classification number: H01L23/66 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1423 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/30111 ,  H01Q1/2283 ,  H01Q1/3233 ,  H01Q23/00 ,  H05K1/0222 ,  H05K1/0243 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/181 ,  H05K2201/09609 ,  H05K2201/10734 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A millimeter wave integrated circuit (IC) chip. The IC chip comprises an IC die and a wire bond ball grid array package encapsulating the IC die. The wire bond ball grid array package comprises a solder ball array, a millimeter wave transmit channel, and a millimeter wave receive channel, wherein each millimeter wave transmit and receive channel electrically couples the IC die to a signal ball of the solder ball array and is configured to resonate at an operating frequency band of the millimeter wave IC chip.