公开(公告)号：US20200212536A1

公开(公告)日：2020-07-02

申请号：US16404810

申请日：2019-05-07

Applicant: Texas Instruments Incorporated

Inventor： Vikas Gupta ,  Sadia Naseem ,  Meysam Moallem

IPC: H01Q1/22 ,  H01Q1/38 ,  H01Q1/40 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/66

Abstract: In a described example, a wireless communication device includes an antenna substrate having an antenna on an antenna side surface; a semiconductor die on an device side surface of the antenna substrate, opposite the antenna side surface; and an antenna protection layer covering the antenna and a portion of the antenna side surface of the antenna substrate having a uniform predetermined thickness across the antenna side surface of the antenna substrate within +/−10%.

公开(公告)号：US20200185322A1

公开(公告)日：2020-06-11

申请号：US16213557

申请日：2018-12-07

Applicant: Texas Instruments Incorporated

Inventor： Rongwei Zhang ,  Vikas Gupta

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: In a described example, a packaged device includes a substrate having a device mounting surface with conductive lands having a first thickness spaced from one another on the device mounting surface. A first polymer layer is disposed on the device mounting surface between the conductive lands having a second thickness equal to the first thickness. The conductive lands have an outer surface not covered by the first polymer layer. A second polymer layer is disposed on the first polymer layer, the outer surface of the conductive lands not covered by the second polymer layer. Conductive nanoparticle material is disposed on the outer surface of the conductive lands. A third polymer layer is disposed on the second polymer layer between the conductive nanoparticle material on the conductive lands. At least one semiconductor device die is mounted to the third polymer layer having electrical terminals bonded to the conductive nanoparticle material.

公开(公告)号：US20190304881A1

公开(公告)日：2019-10-03

申请号：US16443653

申请日：2019-06-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rongwei Zhang ,  Vikas Gupta

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.

公开(公告)号：US20180277463A1

公开(公告)日：2018-09-27

申请号：US15973828

申请日：2018-05-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rongwei Zhang ,  Vikas Gupta

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L23/49541 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/743 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/27318 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83855 ,  H01L2224/83951 ,  H01L2224/85203 ,  H01L2224/92247 ,  H01L2924/07811 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.

公开(公告)号：US20170365575A1

公开(公告)日：2017-12-21

申请号：US15690074

申请日：2017-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yong Lin ,  Vikas Gupta ,  Rongwei Zhang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/544 ,  H01L23/31 ,  H01L21/304 ,  H01L23/495 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L24/29 ,  H01L21/304 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/544 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27848 ,  H01L2224/29034 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29169 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal. A method of forming a packaged IC wherein all of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal and a portion of sidewall of the molding compound is solderable metal.

公开(公告)号：US20170162530A1

公开(公告)日：2017-06-08

申请号：US15368413

申请日：2016-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yong Lin ,  Vikas Gupta ,  Rongwei Zhang

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L24/29 ,  H01L21/304 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/544 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27848 ,  H01L2224/29034 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29169 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal. A method of forming a packaged IC wherein all of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal and a portion of sidewall of the molding compound is solderable metal.

公开(公告)号：US20240047226A1

公开(公告)日：2024-02-08

申请号：US18488990

申请日：2023-10-17

Applicant: Texas Instruments Incorporated

Inventor： Sadia Naseem ,  Vikas Gupta

IPC: H01L21/48 ,  H01L23/495

CPC classification number: H01L21/4821 ,  H01L23/49582

Abstract: The disclosed principles provide for implementing low-cost and fast metallic printing processes into the QFN and other no-leads package assembly flow to selectively print solderable material in areas that would otherwise be susceptible to corrosion and thus pose reliability risks. The problem of copper corrosion and poor BLR performance in no-leads packages because of remaining exposed copper areas after package singulation is solved by employing selective metallic printing processes in the assembly flow to coat all risk-prone areas with solder material. For example, for no-leads packages that are formed using printed leadframes, solder can be deposited through inkjet, screen, stencil, or photonic printing into the grooves which are formed after passivating the packages at the strip level. The singulating occurs through the grooves having solder printed therein, and results in wettable upper and sidewall surfaces of the outer ends of the leadframe for each package.

公开(公告)号：US10910705B2

公开(公告)日：2021-02-02

申请号：US16447419

申请日：2019-06-20

Applicant: Texas Instruments Incorporated

Inventor： Vikas Gupta ,  Athena Lin ,  Juan Alejandro Herbsommer

IPC: H01Q1/38 ,  H01L23/66 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/15 ,  H01L21/56 ,  H01Q1/22 ,  H04B1/40 ,  H01Q1/24

Abstract: An antenna-in-package (AiP) device includes a substrate stack having a ceramic substrate attached to an organic substrate, where a dielectric constant of the ceramic substrate is higher than a dielectric constant of the organic substrate. An antenna is on a top side of the ceramic substrate. An integrated circuit (IC) die is flip chip attached to a bottom side of the ceramic substrate or to a top surface of the organic substrate. The IC die includes a radio circuit including at least a transmitter, and there is at least one interconnect for coupling the radio circuit to the antenna.

公开(公告)号：US20200381390A1

公开(公告)日：2020-12-03

申请号：US16423104

申请日：2019-05-27

Applicant: Texas Instruments Incorporated

Inventor： Rongwei Zhang ,  James Huckabee ,  Vikas Gupta

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/544 ,  H01L21/78 ,  H01L21/304 ,  H01L21/48 ,  H01L21/56

Abstract: A leadless integrated circuit (IC) package includes a spaced apart plurality of lead terminals on at least two sides of the leadless IC package, and an IC die including a substrate having at least a semiconductor surface including circuitry coupled to bond pads with the bond pads having bonding features thereon. The bonding features are flip chip bonded to the plurality of lead terminals. Mold compound is above the IC die and between adjacent lead terminals. The lead terminals and the substrate both extend out to have exposed surfaces at edges of the leadless IC package, and the lead terminals also provide a back side bondable contact.

公开(公告)号：US20200083149A1

公开(公告)日：2020-03-12

申请号：US16681221

申请日：2019-11-12

Applicant: Texas Instruments Incorporated

Inventor： Vikas Gupta ,  Daniel Yong Lin

IPC: H01L23/495 ,  H01L23/31

Abstract: A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.