TOUCH PANEL
    22.
    发明申请
    TOUCH PANEL 审中-公开
    触控面板

    公开(公告)号:US20130269991A1

    公开(公告)日:2013-10-17

    申请号:US13549174

    申请日:2012-07-13

    CPC classification number: G06F3/044 G02B3/0056 G02B3/0075 G06F3/045

    Abstract: Disclosed herein is a touch panel. A touch panel 100 according to a preferred embodiment of the present invention is configured to include a first transparent substrate 110, electrode patterns 120 formed on the first transparent substrate 110, a second transparent substrate 130 disposed more outwardly than the first transparent substrate 110, and micro lenses 140 formed on the second transparent substrate 130 to correspond to the electrode patterns 120 so as to focus an erected virtual image I of the electrode patterns 120 having magnification of 1 or less thereon. By this configuration, a user 150 recognizes the erected virtual images I of the electrode pattern 120 with the reduced magnification of 1 or less through the micro lenses 140, thereby improving the visibility of the touch panel 100.

    Abstract translation: 这里公开了触摸面板。 根据本发明的优选实施例的触摸面板100被配置为包括第一透明基板110,形成在第一透明基板110上的电极图案120,比第一透明基板110更向外设置的第二透明基板130,以及 形成在第二透明基板130上以对应于电极图案120的微透镜140,以便聚焦其上具有1或更小的放大倍数的电极图案120的竖立虚像I。 通过这种配置,用户150通过微透镜140以缩小的1倍或更小的倍率来识别电极图案120的竖立虚像I,从而提高触摸面板100的可见度。

    SEMICONDUCTOR DEVICE WITH OTP MEMORY CELL
    24.
    发明申请
    SEMICONDUCTOR DEVICE WITH OTP MEMORY CELL 失效
    具有OTP存储单元的半导体器件

    公开(公告)号:US20120120707A1

    公开(公告)日:2012-05-17

    申请号:US13249524

    申请日:2011-09-30

    Applicant: Tae Hoon KIM

    Inventor: Tae Hoon KIM

    CPC classification number: G11C17/12

    Abstract: A semiconductor device with an OTP memory cell includes a first MOS transistor having a first gate terminal connected to a first line, and a first terminal connected to a first node, a second MOS transistor having a second gate terminal connected to a second line, and a first terminal connected to the first node, and a third MOS transistor having a gate terminal connected to a three line, and a first terminal of the third MOS transistor connected to the first node.

    Abstract translation: 具有OTP存储单元的半导体器件包括具有连接到第一线的第一栅极端子和与第一节点连接的第一端子的第一MOS晶体管,具有与第二线路连接的第二栅极端子的第二MOS晶体管,以及 连接到第一节点的第一端子和连接到三线的栅极端子的第三MOS晶体管,以及连接到第一节点的第三MOS晶体管的第一端子。

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