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    Semiconductor integrated circuit
    21.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US08692585B2

    公开(公告)日：2014-04-08

    申请号：US13243351

    申请日：2011-09-23

    Applicant: Tae Jin Kang

    Inventor： Tae Jin Kang

    IPC: H03B1/00 ,  H03K3/00

    CPC classification number: G11C7/1057 ,  G11C7/1051 ,  H03K19/018521 ,  H03K19/018585

    Abstract: A semiconductor integrated circuit includes a first output driver configured to drive a first comparison signal, which is generated by comparing a voltage of a pad coupled to an external resistor with an upper-limit reference voltage, according to drivability determined by a pull-up code and a pull-down code, and output the driven signal as first output data; and a second output driver configured to drive a second comparison signal, which is generated by comparing the voltage of the pad with a lower-limit reference voltage, according to the drivability determined by the pull-up code and the pull-down code, and output the driven signal as second output data.

    Abstract translation: 半导体集成电路包括：第一输出驱动器，被配置为驱动第一比较信号，该第一比较信号是通过将耦合到外部电阻器的焊盘的电压与上限参考电压进行比较而产生的，根据由上拉代码确定的驱动能力 和下拉代码，并将驱动信号作为第一输出数据输出; 以及第二输出驱动器，被配置为根据由所述上拉代码和所述下拉码确定的驾驶性能来驱动通过将所述垫的电压与下限参考电压进行比较而产生的第二比较信号，以及 输出驱动信号作为第二输出数据。

    Clock control circuit and clock generation circuit including the same
    22.
    发明授权
    Clock control circuit and clock generation circuit including the same 有权
    时钟控制电路和时钟发生电路包括相同的

    公开(公告)号：US08379475B2

    公开(公告)日：2013-02-19

    申请号：US12824864

    申请日：2010-06-28

    Applicant: Tae Jin Kang

    Inventor： Tae Jin Kang

    IPC: G11C8/00

    CPC classification number: G11C8/18 ,  G11C7/1018 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222

    Abstract: A clock control circuit is presented for reducing unnecessary current consumption. The clock control circuit includes a write enable signal generation unit and a clock enable signal generation unit. The write enable signal generation unit is configured to generate a first write enable signal, which is enabled during a predetermined time period after a write command is inputted, in response to first and second burst signals and a write signal including a pulse generated in response to the write command. The clock enable signal generation unit is configured to generate a clock enable signal, which is enabled during a write operation period, in response to the first write signal and the first write enable signal.

    Abstract translation: 提出了一种时钟控制电路，用于减少不必要的电流消耗。 时钟控制电路包括写使能信号生成单元和时钟使能信号生成单元。 写入使能信号生成单元被配置为响应于第一和第二突发信号而生成第一写入使能信号，该第一写入使能信号在写入命令被输入之后的预定时间段期间被使能，并且写入信号包括响应于 写命令。 时钟使能信号生成单元被配置为响应于第一写入信号和第一写入使能信号而生成在写入操作期间使能的时钟使能信号。

    Clock signal generating circuit and data output apparatus using the same
    24.
    发明授权
    Clock signal generating circuit and data output apparatus using the same 有权
    时钟信号发生电路和使用其的数据输出装置

    公开(公告)号：US07990784B2

    公开(公告)日：2011-08-02

    申请号：US12156859

    申请日：2008-06-05

    Applicant: Tae Jin Kang

    Inventor： Tae Jin Kang

    IPC: G11C17/00

    CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2254 ,  H03K5/131

    Abstract: A semiconductor memory device having a clock signal generating circuit which is capable of controlling a data output in compliance with PVT fluctuation by controlling a output timing of rising and falling clock signal based on a fuse cutting is described. The clock signal generating circuit includes a fuse unit for generating first and second fuse signals based on fuse cutting of fuses, a control signal generating unit for generating first and second fuse signals in response to the fuse signals, a clock signal delaying unit for generating a delayed clock signal by delaying the external clock signal by a delay section specified by the control signals, and a clock generating unit for generating a first internal clock signal in synchronization with a rising edge of the delayed clock signal and for generating a second internal clock signal in synchronization with a falling edge of the delayed clock signal.

    Abstract translation: 描述了具有时钟信号发生电路的半导体存储器件，该时钟信号产生电路能够通过基于熔丝切断来控制上升和下降时钟信号的输出定时来控制符合PVT波动的数据输出。 时钟信号发生电路包括：熔丝单元，用于基于熔丝的熔丝切割产生第一和第二熔丝信号;控制信号产生单元，用于响应于熔丝信号产生第一和第二熔丝信号;时钟信号延迟单元， 延迟时钟信号，通过由控制信号指定的延迟部分延迟外部时钟信号;以及时钟产生单元，用于与延迟时钟信号的上升沿同步地产生第一内部时钟信号，并产生第二内部时钟信号 与延迟的时钟信号的下降沿同步。

    Circuit for generating read and signal and circuit for generating internal clock using the same
    25.
    发明授权
    Circuit for generating read and signal and circuit for generating internal clock using the same 有权
    用于产生读和信号和电路的电路，用于产生使用其的内部时钟

    公开(公告)号：US07952957B2

    公开(公告)日：2011-05-31

    申请号：US12455594

    申请日：2009-06-04

    Applicant: Tae Jin Kang

    Inventor： Tae Jin Kang

    IPC: G11C7/10 ,  G11C11/4193 ,  G11C8/16

    CPC classification number: G11C7/22 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076

    Abstract: A circuit for generating a read end signal includes a clock transferring unit which receives a clock signal, a write/read status signal and an all bank precharge signal and outputs a delayed clock signal, a read signal detecting unit which receives a read pulse signal and the delayed clock signal and generates a read detection signal having a pulse width corresponding to a certain clock, and a read end signal generating unit which receives a first signal, the delayed clock signal and the read detection signal and generates a read end signal.

    Abstract translation: 用于产生读取结束信号的电路包括时钟传送单元，其接收时钟信号，写入/读取状态信号和全部存储体预充电信号并输出​​延迟的时钟信号;读取信号检测单元，其接收读取的脉冲信号;以及 延迟的时钟信号并产生具有对应于某个时钟的脉冲宽度的读出检测信号，以及读出结束信号产生单元，其接收第一信号，延迟的时钟信号和读取的检测信号，并产生读出结束信号。

    Repeater of global input/output line
    26.
    发明授权
    Repeater of global input/output line 有权
    全球输入/输出线路中继器

    公开(公告)号：US07924634B2

    公开(公告)日：2011-04-12

    申请号：US12217203

    申请日：2008-07-01

    Applicant: Tae Jin Kang ,  Seung Hyun Ryu

    Inventor： Tae Jin Kang ,  Seung Hyun Ryu

    IPC: G11C7/10

    CPC classification number: H04B1/48

    Abstract: A repeater of a global input/output line includes a data transmitter including first and second drivers for outputting data signals of the global input/output line through different transmission routes in response to a transmission direction control signal, and a third driver for driving the global input/output line in response to an output signal of the data transmitter.

    Abstract translation: 全局输入/输出线的中继器包括数据发射器，其包括用于响应于传输方向控制信号通过不同传输路由输出全局输入/输出线的数据信号的第一和第二驱动器，以及用于驱动全局 响应于数据发射器的输出信号的输入/输出线。

    Shift circuit capable of reducing current consumption by controlling latch operation
    28.
    发明申请
    Shift circuit capable of reducing current consumption by controlling latch operation 审中-公开
    移位电路能够通过控制闩锁操作来减少电流消耗

    公开(公告)号：US20090185654A1

    公开(公告)日：2009-07-23

    申请号：US12317217

    申请日：2008-12-18

    Applicant: Tae Jin Kang

    Inventor： Tae Jin Kang

    IPC: G11C19/00

    CPC classification number: G11C19/00 ,  G11C19/28

    Abstract: Disclosed is a shift circuit capable of reducing current consumption and circuit area and increasing the operation speed. The shift circuit includes a transfer unit for transferring input data to a first node in response to a clock signal, and a latch unit for latching the data on the first node in response to a clock signal.

    Abstract translation: 公开了一种能够减少电流消耗和电路面积并提高操作速度的移位电路。 移位电路包括用于响应于时钟信号将输入数据传送到第一节点的传送单元和用于响应于时钟信号将数据锁存在第一节点上的锁存单元。

    Bank selectable parallel test circuit and parallel test method thereof
    29.
    发明授权
    Bank selectable parallel test circuit and parallel test method thereof 有权
    银行可选并行测试电路及其并行测试方法

    公开(公告)号：US07136315B2

    公开(公告)日：2006-11-14

    申请号：US11085173

    申请日：2005-03-22

    Applicant: Tae Jin Kang

    Inventor： Tae Jin Kang

    IPC: G11C29/00

    CPC classification number: G11C8/12 ,  G11C29/26 ,  G11C2029/2602

    Abstract: A parallel test circuit performs a selective test on a specific bank. The bank selectable parallel test circuit comprises a bank selecting control unit and a plurality of bank selecting units. The bank selecting control unit outputs a test mode control signal for selecting a test mode in response to a parallel test signal for controlling a parallel test and a compression test signal for controlling bank selection in the parallel test. Each of the plurality of bank selecting units, which correspond one by one to banks, selectively activates the corresponding banks in response to the test mode control signal and a bank selecting control signal.

    Abstract translation: 并行测试电路对特定的银行进行选择性测试。 存储体可选并行测试电路包括存储体选择控制单元和多个存储体选择单元。 存储体选择控制单元响应用于并行测试的并行测试信号和用于在并行测试中控制存储体选择的压缩测试信号，输出用于选择测试模式的测试模式控制信号。 响应于测试模式控制信号和存储体选择控制信号，对应于一个一个存储体的多个存储体选择单元中的每一个选择性地激活相应的存储体。

    Semiconductor device for reducing the number of probing pad used during wafer test and method for testing the same
    30.
    发明授权
    Semiconductor device for reducing the number of probing pad used during wafer test and method for testing the same 有权
    用于减少在晶片测试期间使用的探测器的数量的半导体器件及其测试方法

    公开(公告)号：US07002364B2

    公开(公告)日：2006-02-21

    申请号：US10738691

    申请日：2003-12-17

    Applicant: Tae Jin Kang ,  Woon Bok Lee

    Inventor： Tae Jin Kang ,  Woon Bok Lee

    IPC: G01R31/28

    CPC classification number: G01R31/3172 ,  G01R31/31715 ,  G01R31/318505 ,  G01R31/318511

    Abstract: The present invention relates to a semiconductor device and a method for testing the same capable of reducing the number of probing pads used during wafer test. The semiconductor device includes a select circuit connected between a plurality of internal circuits to be tested and a single probing pad, for transmitting test signals inputted from the probing pads to any one of the plurality of the internal circuits according to a test mode signal generated in a wafer test mode. It is possible to reduce the number of the probing pads in the integrated circuit used for connection to a probe for contact of a probe card during wafer test. It is therefore possible to reduce test time.

    Abstract translation: 半导体器件及其测试方法技术领域本发明涉及能够减少在晶片测试期间使用的探针焊盘数量的半导体器件及其测试方法。 半导体器件包括连接在待测试的多个内部电路和单个探测焊盘之间的选择电路，用于根据在多个内部电路中产生的测试模式信号将从探测焊盘输入的测试信号发送到多个内部电路中的任何一个 晶圆测试模式。 在晶片测试期间，可以减少用于与用于探针卡接触的探针连接的集成电路中的探测器的数量。 因此可以减少测试时间。

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