公开(公告)号：US20180164695A1

公开(公告)日：2018-06-14

申请号：US15689244

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Hsien HSIEH ,  Wen-Li CHENG ,  Pai-Wei WANG ,  Ru-Gun LIU ,  Chih-Ming LAI

IPC: G03F7/20 ,  G06F17/50 ,  G03F1/22 ,  G03F1/36

CPC classification number: G03F7/70283 ,  G03F1/22 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G03F7/705 ,  G06F17/5045 ,  G06F17/5081

Abstract: A multiple patterning decomposition method for IC is provided. Features of layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a plurality of first and second links between the nodes. First and second pseudo colors are assigned to a pair of nodes of each first link. The second links having a pair of nodes both corresponding to the first or second pseudo color are identified. The nodes of the first links are uncolored. A first real color is assigned to the two uncolored nodes of the identified second links in each of the networks. A second real color is assigned to the uncolored nodes connected to the nodes corresponding to the first real color through the first links. First and second masks are formed according to the nodes corresponding to the first and second real colors, respectively.

公开(公告)号：US20230187434A1

公开(公告)日：2023-06-15

申请号：US18167651

申请日：2023-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen YOUNG ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Jiann-Tyng TZENG ,  Shun-Li CHEN ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Chun-Kuang CHEN ,  Ru-Gun LIU

IPC: H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  G06F30/394

CPC classification number: H01L27/0207 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823425 ,  H01L21/823431 ,  H01L23/485 ,  G06F30/394 ,  H01L23/528

Abstract: A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

公开(公告)号：US20230091869A1

公开(公告)日：2023-03-23

申请号：US18053021

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Ching-Wei TSAI ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kuo-Cheng CHIANG ,  Ru-Gun LIU ,  Wei-Hao WU ,  Yi-Hsiung LIN ,  Chia-Hao CHANG ,  Lei-Chun CHOU

IPC: H01L29/78 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66 ,  H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20210334446A1

公开(公告)日：2021-10-28

申请号：US17365897

申请日：2021-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Wei PENG ,  Chih-Ming LAI ,  Jiann-Tyng TZENG

IPC: G06F30/392 ,  H01L23/538

Abstract: A device includes a first cell, a second cell, and first isolation portions. The second cell is adjacent the first cell. The first and second cells are arranged in a first direction, and the first cell includes first and second conductive structures. The first conductive structures extend in the first direction. Each of the first conductive structures has a first end facing the second cell. The second conductive structures extend in the first direction. The first and second conductive structures are alternately arranged in a second direction different from the first direction. The first isolation portions are respectively abutting the first ends of the first conductive structures. Two of the first isolation portions are misaligned with each other in the second direction.

公开(公告)号：US20200176267A1

公开(公告)日：2020-06-04

申请号：US16688681

申请日：2019-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Min HSIAO ,  Chih-Ming LAI ,  Chien-Wen LAI ,  Ya Hui CHANG ,  Ru-Gun LIU

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

公开(公告)号：US20200174380A1

公开(公告)日：2020-06-04

申请号：US16698044

申请日：2019-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Ting HUANG ,  Tung-Chin WU ,  Shih-Hsiang LO ,  Chih-Ming LAI ,  Jue-Chin YU ,  Ru-Gun LIU ,  Chin-Hsiang LIN

IPC: G03F7/20 ,  G06F16/23 ,  G06N3/04 ,  G06N3/08 ,  G06F30/392 ,  G06F30/398

Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.

公开(公告)号：US20160268244A1

公开(公告)日：2016-09-15

申请号：US15159692

申请日：2016-05-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen YOUNG ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Jiann-Tyng TZENG ,  Shun-Li CHEN ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Chun-Kuang CHEN ,  Ru-Gun LIU

IPC: H01L27/02 ,  H01L23/535 ,  G06F17/50 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor structure includes following operations. Gate structures are arranged above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure. The first and second active regions are spaced apart by the non-active region. Contacts are arranged above the first and second active regions. At least one gate via is arranged above the first active region or the second active region. The at least one gate via is electrically coupled with the gate structures. At least one local interconnect is selectively arranged over the non-active region, to couple at least one of the contacts above the first active region to at least one of the contacts above the second active region.

Abstract translation: 一种形成半导体结构的方法包括以下操作。 栅极结构布置在半导体结构的衬底的第一有源区，第二有源区和非有源区的上方。 第一和第二有源区域被非有源区域隔开。 触点设置在第一和第二活动区域的上方。 至少一个栅极通孔布置在第一有源区或第二有源区的上方。 至少一个栅极通孔与栅极结构电耦合。 至少一个局部互连选择性地布置在非有源区上方，以将第一有源区上方的至少一个触点耦合到第二有源区上方的至少一个触点。

公开(公告)号：US20160064322A1

公开(公告)日：2016-03-03

申请号：US14476349

申请日：2014-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Yung-Sung YEN ,  Kam-Tou SIO ,  Tsong-Hua OU ,  Chun-Kuang CHEN ,  Ru-Gun LIU ,  Shu-Hui SUNG ,  Charles Chew-Yuen YOUNG

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/118

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. In addition, some of the metal layers include metal lines extending in the first direction, and some of the metal layers include metal lines extending in a second direction substantially perpendicular to the first direction. Furthermore, the gate structures follow the following equation: 0.2   P gate   min + 0.35   L gate   min + 0.3   H gate   min - 20 0.2   L gate   min + 0.8   H gate   min - 5 × 0.3   L gate   min + 0.3   H gate   min + 5 38 ≤ 0.32 Pgate min is the minimum value among gate pitches of the gate structures. Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.

Abstract translation: 提供半导体结构。 半导体结构包括沿着形成在衬底上的第一方向延伸的多个栅极结构以及与衬底上的栅极结构相邻形成的触点。 半导体结构还包括形成在栅极结构上的多个金属层。 此外，一些金属层包括在第一方向上延伸的金属线，并且一些金属层包括沿基本上垂直于第一方向的第二方向延伸的金属线。 此外，栅极结构遵循以下公式：0.2P门min + 0.35min min min H门槛最小 - 5×0.3L门min + 0.3H门min + 5 38≤0.32 P门min是门结构的栅间距中的最小值。 Lgate min是门结构的栅极长度之间的最小值。 Hgate min是门结构栅极高度的最小值。