公开(公告)号：US09400866B2

公开(公告)日：2016-07-26

申请号：US14833260

申请日：2015-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Xiang Lee ,  Li-Chung Hsu ,  Shih-Hsien Yang ,  Ho Che Yu ,  King-Ho Tam ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/02 ,  G06F2217/78 ,  G06F2217/84

Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identities a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

Abstract translation: 一种方法包括提供一种非暂时的机器可读存储介质，其存储至少部分先前采集的集成电路（IC）布局的部分网表，其表示用于制造具有IC布局的IC的一组光掩模， 该IC满足第一规格值。 计算机识别IC布局中的多个第一设备的正确子集，使得经修改的IC布局中的第二设备的第一设备的适当子集的替换满足与第一规范值不同的第二规范值。 至少一个布局掩模被生成并存储在至少一个非暂时机器可读存储介质中，可由用于形成至少一个附加光掩模的工具访问，使得该组光掩模和至少一个附加光掩模可用于制造 一个IC根据修订的IC布局。

公开(公告)号：US12175180B2

公开(公告)日：2024-12-24

申请号：US18232742

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chung Hsu ,  Yen-Pin Chen ,  Sung-Yen Yeh ,  Jerry Chang-Jui Kao ,  Chung-Hsing Wang

IPC: G06F30/392 ,  G06F30/367 ,  G06F113/18 ,  G06F119/06

Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

公开(公告)号：US11783106B2

公开(公告)日：2023-10-10

申请号：US17227748

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ravi Babu Pittu ,  Chung-Hsing Wang ,  Sung-Yen Yeh ,  Li Chung Hsu

IPC: G06F9/455 ,  G06F30/3312 ,  G06F30/39 ,  G06F30/367 ,  G06F119/12

CPC classification number: G06F30/3312 ,  G06F30/367 ,  G06F30/39 ,  G06F2119/12

Abstract: A method and system for manufacturing a circuit is disclosed. In some embodiments, the system includes: at least one processor configured to: generate a first timing library for a first set of circuit elements for a first set of input parameters based on device characteristics for each of the circuit elements in the first set of circuit elements, and storing the determined device characteristics in a database; and generating a second timing library for a second set of circuit elements for a second set of input parameters based on device characteristics previously stored in the database for a first subset of the second set of circuit elements and determining device characteristics for a second subset of the second set of circuit elements using one of an aging simulation or a stress simulation; and a circuit generation system, coupled to the at least one processor, the circuit generation system configured to form a circuit on a substrate, wherein the circuit includes at least one of the first set of circuit elements or the second set of circuit elements.

公开(公告)号：US11720738B2

公开(公告)日：2023-08-08

申请号：US17315023

申请日：2021-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Hua Liu ,  Yun-Xiang Lin ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F30/30 ,  G06F30/398 ,  G06F30/367 ,  G06F30/20 ,  G06F30/39 ,  G06F119/10 ,  G06F30/392 ,  G06F119/18 ,  G06F111/20

CPC classification number: G06F30/398 ,  G06F30/20 ,  G06F30/367 ,  G06F30/39 ,  G06F30/392 ,  G06F2111/20 ,  G06F2119/10 ,  G06F2119/18

Abstract: A system includes a library, a processor and an output interface. The library contains at least one leakage lookup table related to leakage current values for different cell abutment cases of abutted cells in a semiconductor device. The cell abutment cases are associated with terminal types of cell edges of the abutted cells. The processor is configured to perform an analysis to detect boundaries between the abutted cells, identify attributes associated with the terminal types of the cell edges, identify the cell abutment cases based on the attributes, and calculate maximal boundary leakages between the abutted cells based on leakage current values associated with the cell abutment cases and leakage probabilities associated with the cell abutment cases. The output interface is for outputting boundary leakages corresponding to the maximal boundary leakages in the semiconductor device. A method is also disclosed herein.

公开(公告)号：US11593546B2

公开(公告)日：2023-02-28

申请号：US17404511

申请日：2021-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuang-Hung Chang ,  Yuan-Te Hou ,  Chung-Hsing Wang ,  Yung-Chin Hou

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/20 ,  G06F30/327 ,  H01L23/528 ,  H01L27/088 ,  G06F30/394

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.

公开(公告)号：US20210334447A1

公开(公告)日：2021-10-28

申请号：US17370717

申请日：2021-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chung Hsu ,  Yen-Pin Chen ,  Sung-Yen Yeh ,  Jerry Chang-Jui Kao ,  Chung-Hsing Wang

IPC: G06F30/392 ,  G06F30/367

Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

公开(公告)号：US20210326509A1

公开(公告)日：2021-10-21

申请号：US17363669

申请日：2021-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung LIN ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F30/392 ,  G06F30/39

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

公开(公告)号：US20200226316A1

公开(公告)日：2020-07-16

申请号：US16837449

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung LIN ,  Chung-Hsing Wang ,  Yuan-Te Hou

IPC: G06F30/392

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.

公开(公告)号：US10515944B2

公开(公告)日：2019-12-24

申请号：US16122762

申请日：2018-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fong-Yuan Chang ,  Kuo-Nan Yang ,  Chung-Hsing Wang ,  Lee-Chung Lu ,  Sheng-Fong Chen ,  Po-Hsiang Huang ,  Hiranmay Biswas ,  Sheng-Hsiung Chen ,  Aftab Alam Khan

IPC: H01L29/06 ,  H01L27/02 ,  H01L23/522 ,  G06F17/50 ,  H01L27/118

Abstract: An integrated circuit includes a cell layer, a first metal layer, and a first conductive via. The cell layer includes first and second cells, each of which is configured to perform a circuit function. The first metal layer is above the cell layer and includes a first conductive feature that extends from the first cell into the second cell and that is configured to receive a supply voltage. A first conductive via interconnects the cell layer and the metal layer.

公开(公告)号：US20190006346A1

公开(公告)日：2019-01-03

申请号：US16125965

申请日：2018-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L27/02 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/06 ,  H01L21/768 ,  H01L23/50

Abstract: A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active device layer over and in contact with the first interconnect structure, a first switch in the second active device layer, a second interconnect structure over and in contact with the second active device layer, a third active device layer over and in contact with the second interconnect structure, a second power circuit in the third active device layer and a third interconnect structure over and in contact with the third active device layer and connected to a power source, wherein the power source is configured to provide power to the first power circuit through the first switch.