公开(公告)号：US08872138B2

公开(公告)日：2014-10-28

申请号：US13771112

申请日：2013-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ying Lu ,  Sung-Po Yang ,  Ding-I Liu ,  Kuo-Shu Tseng ,  Chung-Wen Chang

IPC: G21K5/04 ,  B05D3/06

CPC classification number: B05D3/067 ,  H01L21/67115 ,  H01L21/6776

Abstract: A UV curing system includes an enclosure defining an interior, a UV radiation source disposed within the interior of the enclosure, and a first window disposed within the interior of the enclosure. The first window creates a barrier that separates the UV radiation source and a processing chamber. A second window is disposed within the interior of the enclosure at a distance from the first window to define a gas channel. The second window defines a plurality of openings such that the gas channel is in fluid communication with the processing chamber. A gas inlet conduit is in fluid communication with the gas channel and is configured to introduce a cooling gas into the gas channel. A gas outlet is in fluid communication with the processing chamber and is configured to remove gas from the processing chamber.

Abstract translation: UV固化系统包括限定内部的外壳，设置在外壳内部的UV辐射源以及设置在外壳内部的第一窗口。 第一个窗口创建一个隔离UV辐射源和一个处理室的屏障。 第二窗口设置在与第一窗口相距一定距离的外壳的内部，以限定气体通道。 第二窗口限定多个开口，使得气体通道与处理室流体连通。 气体入口导管与气体通道流体连通，并且构造成将冷却气体引入气体通道。 气体出口与处理室流体连通并且被配置为从处理室去除气体。

公开(公告)号：US20140306294A1

公开(公告)日：2014-10-16

申请号：US13860765

申请日：2013-04-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Po-Chang Chen ,  Po-Hsiung Leu ,  Ding-I Liu

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L29/0653 ,  H01L21/0214 ,  H01L21/02219 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/762 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure relates to an integrated chip IC having transistors with structures separated by a flowable dielectric material, and a related method of formation. In some embodiments, an integrated chip has a semiconductor substrate and an embedded silicon germanium (SiGe) region extending as a positive relief from a location within the semiconductor substrate to a position above the semiconductor substrate. A first gate structure is located at a position that is separated from the embedded SiGe region by a first gap. A flowable dielectric material is disposed between the gate structure and the embedded SiGe region and a pre-metal dielectric (PMD) layer disposed above the flowable dielectric material. The flowable dielectric material provides for good gap fill capabilities that mitigate void formation during gap fill between the adjacent gate structures.

Abstract translation: 本公开内容涉及具有由可流动介电材料分离的结构的晶体管的集成芯片IC以及相关的形成方法。 在一些实施例中，集成芯片具有半导体衬底和嵌入硅锗（SiGe）区域，该半导体衬底和半导体衬底上的位置从半导体衬底内的位置以正电位延伸。 第一栅极结构位于通过第一间隙与嵌入的SiGe区分离的位置。 在栅极结构和嵌入的SiGe区域之间设置可流动介电材料，以及设置在可流动介电材料之上的预金属电介质（PMD）层。 可流动介电材料提供良好的间隙填充能力，以减轻相邻栅极结构之间的间隙填充期间的空隙形成。

公开(公告)号：US11967522B2

公开(公告)日：2024-04-23

申请号：US17660508

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-Nan Lin ,  Chia-Yu Wu ,  Kai-Shiung Hsu ,  Ding-I Liu

IPC: H01L21/768 ,  C23F1/12 ,  H01L21/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76829 ,  C23F1/12 ,  H01L21/02178 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53295

Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.

公开(公告)号：US20220254679A1

公开(公告)日：2022-08-11

申请号：US17660508

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-Nan Lin ,  Chia-Yu Wu ,  Kai-Shiung Hsu ,  Ding-I Liu

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522 ,  C23F1/12

Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.

公开(公告)号：US11264273B2

公开(公告)日：2022-03-01

申请号：US16941040

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jen Chen ,  Kai-Shiung Hsu ,  Ding-I Liu ,  Jyh-nan Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

公开(公告)号：US20210233805A1

公开(公告)日：2021-07-29

申请号：US16941040

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jen CHEN ,  Kai-Shiung Hsu ,  Ding-I Liu ,  Jyh-nan Lin

IPC: H01L21/768 ,  H01L23/522

Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

公开(公告)号：US20210066122A1

公开(公告)日：2021-03-04

申请号：US16890413

申请日：2020-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-Nan Lin ,  Chia-Yu Wu ,  Kai-Shiung Hsu ,  Ding-I Liu

IPC: H01L21/768 ,  H01L21/02 ,  C23F1/12 ,  H01L23/532 ,  H01L23/522

Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the n etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.

公开(公告)号：US20200073258A1

公开(公告)日：2020-03-05

申请号：US16547301

申请日：2019-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Chiu ,  Ding-I Liu ,  Yu-Ying Lu

IPC: G03F7/20

Abstract: An Equipment Front End Module (EFEM) having a Front Opening Unified Pod (FOUP) dock and a tool access port, includes a robotic wafer handling system configured to transfer silicon wafers between a FOUP coupled to the FOUP dock and a process tool positioned for access via the tool access port. An air curtain system inside the EFEM is positioned to produce an air curtain across the tool access port while the port is open, acting to isolate the interior of the EFEM from the tool environment, and prevent passage of airborne contaminants into the EFEM via the access port.

公开(公告)号：US09859113B2

公开(公告)日：2018-01-02

申请号：US14689647

申请日：2015-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Yang Li ,  Chun-Sheng Wu ,  Ding-I Liu ,  Yi-Fang Li

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L21/02274 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The semiconductor device structure includes spacers over opposite sidewalls of the gate stack. The spacers and the gate stack surround a recess over the gate stack. The semiconductor device structure includes a first insulating layer over the gate stack and an inner wall of the recess. The semiconductor device structure includes a second insulating layer over the first insulating layer. Materials of the first insulating layer and the second insulating layer are different, and a first thickness of the first insulating layer is less than a second thickness of the second insulating layer.

公开(公告)号：US20170283948A1

公开(公告)日：2017-10-05

申请号：US15088064

申请日：2016-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Chiu ,  Ding-I Liu ,  Chin-Feng Lin ,  Po-Hsiung Leu

IPC: C23C16/455 ,  H01J37/32 ,  C23C16/505

Abstract: A showerhead is configured to be mounted inside a processing chamber and provide a processing gas onto a semiconductor wafer inside the processing chamber. The showerhead includes a supply plenum, a faceplate, and an electrode plate assembly. The faceplate is disposed at a side of the supply plenum. The electrode plate assembly is disposed between a gas source and the supply plenum. The electrode plate assembly includes a first plate having a unitary construction and having a plurality of first gas holes, and a second plate having a unitary construction and having a plurality of second gas holes. The second plate is located between the first plate and the supply plenum and separated from the first plate. The plurality of second gas holes are partially overlapped but misaligned with the plurality of first gas holes. A semiconductor apparatus having the same and a semiconductor process are also provided.