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    RRAM Cell with Bottom Electrode
    21.
    发明申请
    RRAM Cell with Bottom Electrode 有权
    带底电极的RRAM电池

    公开(公告)号：US20150295172A1

    公开(公告)日：2015-10-15

    申请号：US14252111

    申请日：2014-04-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Yu-Wen Liao ,  Wen-Ting Chu ,  Yu-Hsing Chang ,  Ru-Liang Lee

    IPC: H01L45/00 ,  H01L23/538

    CPC classification number: H01L45/1253 ,  H01L23/538 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom and top electrodes, and thereby provides for low leakage current for the RRAM cell.

    Abstract translation: 本公开涉及具有底部电极的电阻随机存取存储器（RRAM）单元，其在不使用绝缘侧壁间隔件的情况下提供RRAM单元内的低泄漏电流，以及相关联的形成方法。 在一些实施例中，RRAM单元具有设置在由下层电介质（ILD）层围绕的下金属互连层上的底电极。 底部电介质层设置在下部金属互连层和/或下部ILD层上。 具有可变电阻的电介质数据存储层位于底部电介质层和底部电极之上，并且顶部电极设置在电介质数据存储层上。 将电介质数据存储层放置在底部电介质层上增加了底部和顶部电极之间的泄漏路径距离，从而为RRAM单元提供了低泄漏电流。

    Resistive random access memory structure
    22.
    发明授权
    Resistive random access memory structure 有权

    公开(公告)号：US10475998B2

    公开(公告)日：2019-11-12

    申请号：US14610691

    申请日：2015-01-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

    Inventor： Chern-Yow Hsu ,  Fu-Ting Sung ,  Shih-Chang Liu

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bottom electrode having a first width and a dielectric structure having a second width formed over the bottom electrode. The semiconductor structure further includes a top electrode having a third width formed over the dielectric structure. In addition, the second width of the dielectric structure is greater than the first width of the bottom electrode.

    RRAM cell with bottom electrode
    24.
    发明授权
    RRAM cell with bottom electrode 有权
    带底电极的RRAM电池

    公开(公告)号：US09178144B1

    公开(公告)日：2015-11-03

    申请号：US14252111

    申请日：2014-04-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Yu-Wen Liao ,  Wen-Ting Chu ,  Yu-Hsing Chang ,  Ru-Liang Lee

    IPC: H01L45/00 ,  H01L23/538

    CPC classification number: H01L45/1253 ,  H01L23/538 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom and top electrodes, and thereby provides for low leakage current for the RRAM cell.

    Abstract translation: 本公开涉及具有底部电极的电阻随机存取存储器（RRAM）单元，其在不使用绝缘侧壁间隔件的情况下提供RRAM单元内的低泄漏电流，以及相关联的形成方法。 在一些实施例中，RRAM单元具有设置在由下层电介质（ILD）层围绕的下金属互连层上的底电极。 底部电介质层设置在下部金属互连层和/或下部ILD层上。 具有可变电阻的电介质数据存储层位于底部电介质层和底部电极之上，并且顶部电极设置在电介质数据存储层上。 将电介质数据存储层放置在底部电介质层上增加了底部和顶部电极之间的泄漏路径距离，从而为RRAM单元提供了低泄漏电流。

    REVERSED STACK MTJ
    26.
    发明申请
    REVERSED STACK MTJ 审中-公开

    公开(公告)号：US20200083441A1

    公开(公告)日：2020-03-12

    申请号：US16683568

    申请日：2019-11-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

    IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12

    Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

    REVERSED STACK MTJ
    27.
    发明申请
    REVERSED STACK MTJ 审中-公开

    公开(公告)号：US20170194559A1

    公开(公告)日：2017-07-06

    申请号：US15463500

    申请日：2017-03-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

    IPC: H01L43/08

    CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

    Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

    Reversed Stack MTJ
    29.
    发明申请
    Reversed Stack MTJ 有权
    反转堆叠MTJ

    公开(公告)号：US20150061052A1

    公开(公告)日：2015-03-05

    申请号：US14016343

    申请日：2013-09-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

    IPC: H01L43/12 ,  H01L43/02

    CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

    Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

    Abstract translation: 集成电路器件包括衬底和磁隧道结（MTJ）。 MTJ至少包括钉扎层，阻挡层和自由层。 MTJ形成在衬底的表面上。 在被钉扎层，阻挡层和自由层中，自由层首先形成并且最接近表面。 这使得在蚀刻自由层之前，可以在自由层的周边区域上形成间隔物。 由蚀刻或其它自由层边界限定工艺导致的对自由层的任何损伤通过间隔物保持与隧道结一定距离。

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