公开(公告)号：US11569226B2

公开(公告)日：2023-01-31

申请号：US17129763

申请日：2020-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Chih Wen ,  Han-Ting Tsai ,  Chung-Te Lin

IPC: H01L27/06 ,  H01L21/822 ,  H01L21/768 ,  H01L27/22 ,  H01L23/525 ,  H01L23/522 ,  H01L27/24 ,  H01L45/00 ,  H01L43/12 ,  H01L27/32 ,  H01L21/8234

Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

公开(公告)号：US20200303456A1

公开(公告)日：2020-09-24

申请号：US16896369

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Min Cao ,  Han-Ting Tsai ,  Pin-Cheng Hsu ,  Yen-Chung Ho

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/02

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The modulating layer is configured to reinforce stability of the free layer by magnetically coupled to the free layer.

公开(公告)号：US10734580B2

公开(公告)日：2020-08-04

申请号：US16397871

申请日：2019-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Han-Ting Tsai ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H01L45/00 ,  H01L27/24 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A memory device includes an inter-layer dielectric (ILD) layer, a metallization pattern, an etch stop layer, a metal-containing compound layer, a memory cell, and a bottom electrode via. The metallization pattern is in the ILD layer. The etch stop layer is over the ILD layer. The metal-containing compound layer is over the etch stop layer. The memory cell is over the metal-containing compound layer and includes a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element. The bottom electrode via connects the bottom electrode to the metallization pattern through the metal-containing compound layer and the etch stop layer.

公开(公告)号：US20200105830A1

公开(公告)日：2020-04-02

申请号：US16416529

申请日：2019-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Min Cao ,  Han-Ting Tsai ,  Pin-Cheng Hsu ,  Yen-Chung Ho

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.

公开(公告)号：US10515948B2

公开(公告)日：2019-12-24

申请号：US15941716

申请日：2018-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Chih Wen ,  Han-Ting Tsai ,  Chung-Te Lin

IPC: H01L27/06 ,  H01L21/822 ,  H01L21/768 ,  H01L27/22 ,  H01L23/525 ,  H01L23/522 ,  H01L27/24 ,  H01L45/00 ,  H01L43/12 ,  H01L27/32 ,  H01L21/8234

Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

公开(公告)号：US12219880B2

公开(公告)日：2025-02-04

申请号：US18595256

申请日：2024-03-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Sheng-Chih Lai ,  Han-Ting Tsai ,  Chung-Te Lin

IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

Abstract: A memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. The magnetic tunnel junction pattern is over the bottom electrode contact. The protection insulating layer surrounds the magnetic tunnel junction pattern. The first capping layer surrounds the protection insulating layer. The interlayer insulating layer surrounds the first capping layer. The second capping layer is over the first capping layer and the interlayer insulating layer.

公开(公告)号：US20240381786A1

公开(公告)日：2024-11-14

申请号：US18781095

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Yu-Feng Yin ,  An-Shen Chang ,  Han-Ting Tsai ,  Qiang Fu

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

公开(公告)号：US11990167B2

公开(公告)日：2024-05-21

申请号：US17352658

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Jhih Shen ,  Kuang-I Liu ,  Joung-Wei Liou ,  Jinn-Kwei Liang ,  Yi-Wei Chiu ,  Chin-Hsing Lin ,  Li-Te Hsu ,  Han-Ting Tsai ,  Cheng-Yi Wu ,  Shih-Ho Lin

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85 ,  G01R33/09 ,  G11B5/39

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85 ,  G01R33/098 ,  G11B5/3909 ,  G11C2211/5615

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

公开(公告)号：US11864467B2

公开(公告)日：2024-01-02

申请号：US17461132

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Wu Meng Yu ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Han-Ting Tsai ,  Yu-Jen Chien

IPC: H10N50/01 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H10B61/00 ,  H10N50/80

Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.

公开(公告)号：US11665977B2

公开(公告)日：2023-05-30

申请号：US16887244

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Yu-Feng Yin ,  An-Shen Chang ,  Han-Ting Tsai ,  Qiang Fu

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H01L43/02 ,  H01L27/22 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  H01L27/228 ,  H01L43/12

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.