公开(公告)号：US11177259B2

公开(公告)日：2021-11-16

申请号：US16585267

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure describes a semiconductor device that includes a semiconductor device that includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer on the first gate dielectric layer. The first gate structure also includes a first gate electrode on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, where the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration lower than the first dopant concentration. The second gate structure also includes a second work function layer on the second gate dielectric layer and a second gate electrode on the second work function layer.

公开(公告)号：US20210328064A1

公开(公告)日：2021-10-21

申请号：US17328145

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US20210296503A1

公开(公告)日：2021-09-23

申请号：US17339615

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Chi On Chui ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor structure includes gate spacers disposed over a semiconductor layer, a hafnium-containing dielectric layer, where a first portion of the hafnium-containing dielectric layer having a first thickness is disposed over the semiconductor layer and a second portion of the hafnium-containing dielectric layer having a second thickness is disposed along sidewalls of the gate spacers, and where the first thickness is greater than the second thickness, and a metal gate electrode disposed over the hafnium-containing dielectric layer and between the gate spacers.

公开(公告)号：US11069807B2

公开(公告)日：2021-07-20

申请号：US16515898

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Bo-Feng Young ,  Chi On Chui ,  Chih-Yu Chang ,  Huang-Lin Chao

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US11049937B2

公开(公告)日：2021-06-29

申请号：US16657017

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Chun-I Wu ,  Huang-Lin Chao

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

公开(公告)号：US10998239B2

公开(公告)日：2021-05-04

申请号：US16927145

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chu-An Lee ,  Chen-Hao Wu ,  Peng-Chung Jangjian ,  Chun-Wen Hsiao ,  Teng-Chun Tsai ,  Huang-Lin Chao

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/3105

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. The semiconductor device structure also includes an insulating structure that includes a first insulating layer formed between and separating from the first fin and the second fin, a second insulating layer embedded in the first insulating layer, a first capping layer formed in the first insulating layer to cover a top surface of the second insulating layer, and a second capping layer in the first capping layer.

公开(公告)号：US20200032105A1

公开(公告)日：2020-01-30

申请号：US16456918

申请日：2019-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Hsuan Lee ,  Shen-Nan Lee ,  Chen-Hao Wu ,  Chun-Hung Liao ,  Teng-Chun Tsai ,  Huang-Lin Chao

IPC: C09G1/02 ,  H01L21/321

Abstract: A chemical mechanical polishing (CMP) slurry composition includes an oxidant including one or more oxygen molecules, and an abrasive particle having a core structure encapsulated by a shell structure. The core structure includes a first compound and the shell structure includes a second compound different from the first compound, where a diameter of the core structure is greater than a thickness of the shell structure, and where the first compound is configured to react with the oxidant to form a reactive oxygen species.

公开(公告)号：US12080779B2

公开(公告)日：2024-09-03

申请号：US17408985

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Teng-Chun Tsai ,  Huang-Lin Chao ,  Akira Mineji

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/321 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66515 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L29/45 ,  H01L29/4983 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

公开(公告)号：US20240105813A1

公开(公告)日：2024-03-28

申请号：US18521223

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh Wen Tsau ,  Ziwei Fang ,  Huang-Lin Chao ,  Kuo-Liang Sung

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/56 ,  H01L21/82 ,  H01L23/28 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/56 ,  H01L21/82 ,  H01L23/28 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes an interfacial layer disposed over a semiconductor channel region, a metal oxide layer disposed over the interfacial layer, a high-k gate dielectric layer disposed over the metal oxide layer, a metal halide layer disposed over the high-k gate dielectric layer, and a metal gate electrode disposed over the high-k gate dielectric layer. The metal oxide layer and the interfacial layer form a dipole moment. The metal oxide layer includes a first metal. The metal halide layer includes a second metal different from the first metal.

公开(公告)号：US11915937B2

公开(公告)日：2024-02-27

申请号：US17378017

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Huang-Lin Chao ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/3115 ,  H01L29/66 ,  H01L29/40 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L21/28158 ,  H01L21/3115 ,  H01L27/092 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66439 ,  H01L29/66553

Abstract: A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive material.