中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

38 records (took 0.025 seconds)

    ELECTROSTATIC DISCHARGE (ESD) ARRAY WITH CIRCUIT CONTROLLED SWITCHES
    21.
    发明公开
    ELECTROSTATIC DISCHARGE (ESD) ARRAY WITH CIRCUIT CONTROLLED SWITCHES 审中-公开

    公开(公告)号：US20230395534A1

    公开(公告)日：2023-12-07

    申请号：US18232739

    申请日：2023-08-10

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tao-Yi HUNG ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen

    IPC: H01L23/60 ,  H01L27/02 ,  H02H9/04

    CPC classification number: H01L23/60 ,  H01L27/0266 ,  H01L27/0292 ,  H02H9/046

    Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

    Single-gate-oxide power inverter and electrostatic discharge protection circuit
    24.
    发明授权
    Single-gate-oxide power inverter and electrostatic discharge protection circuit 有权

    公开(公告)号：US11670941B2

    公开(公告)日：2023-06-06

    申请号：US17837948

    申请日：2022-06-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Hung Chen ,  Kuo-Ji Chen ,  Shao-Yu Chou

    IPC: H02H9/04 ,  H03K17/082 ,  H01L27/02

    CPC classification number: H02H9/046 ,  H01L27/0266 ,  H01L27/0285 ,  H03K17/0822

    Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.

    Single-gate-oxide power inverter and electrostatic discharge protection circuit
    26.
    发明授权
    Single-gate-oxide power inverter and electrostatic discharge protection circuit 有权

    公开(公告)号：US11374403B2

    公开(公告)日：2022-06-28

    申请号：US17180345

    申请日：2021-02-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Hung Chen ,  Kuo-Ji Chen ,  Shao-Yu Chou

    IPC: H02H9/04 ,  H03K17/082 ,  H01L27/02

    Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.

    Single-gate-oxide power inverter and electrostatic discharge protection circuit
    27.
    发明授权
    Single-gate-oxide power inverter and electrostatic discharge protection circuit 有权

    公开(公告)号：US10931103B2

    公开(公告)日：2021-02-23

    申请号：US16143315

    申请日：2018-09-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Hung Chen ,  Kuo-Ji Chen ,  Shao-Yu Chou

    IPC: H02H9/04 ,  H03K17/082 ,  H01L27/02

    Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.

    Method and apparatus for forming an integrated circuit with a metalized resistor in a standard cell configuration
    29.
    发明授权
    Method and apparatus for forming an integrated circuit with a metalized resistor in a standard cell configuration 有权
    用于在标准单元结构中用金属化电阻器形成集成电路的方法和装置

    公开(公告)号：US09035393B2

    公开(公告)日：2015-05-19

    申请号：US13779783

    申请日：2013-02-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei Yu Ma ,  Bo-Ting Chen ,  Ting Yu Chen ,  Kuo-Ji Chen ,  Li-Chun Tien

    IPC: H01L27/02 ,  H01L27/06 ,  H01L27/118 ,  H01L49/02

    CPC classification number: H01L27/0288 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0629 ,  H01L27/11807 ,  H01L28/20 ,  H01L28/24

    Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.

    Abstract translation: 集成电路包括半导体器件层，其包括在栅电极线之间具有固定栅电极间距的标准单元配置和在标准单元配置的固定栅电极间距之间由金属形成的电阻。 在一个实施例中，集成电路可以是具有由金属形成的电阻器的交叉域标准单元的充电器件模型（CDM）静电放电（ESD）保护电路。 制造集成电路的方法包括：形成由栅电极间距分开的多个栅极电极线，以形成芯标准电池器件，在栅电极间距内施加至少第一金属层以形成电阻器的一部分，以及 施加至少第二金属层以耦合到第一金属层以形成电阻器的另一部分。

    Backside PN junction diode
    30.
    发明授权
    Backside PN junction diode 有权

    公开(公告)号：US12183736B2

    公开(公告)日：2024-12-31

    申请号：US18356802

    申请日：2023-07-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Kuan-Lun Cheng

    IPC: H01L27/088 ,  H01L27/07 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

    Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

Patent Agency Ranking