公开(公告)号：US20220359489A1

公开(公告)日：2022-11-10

申请号：US17869968

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L25/18

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US20240387341A1

公开(公告)日：2024-11-21

申请号：US18465622

申请日：2023-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Meng-Liang Lin ,  Chieh-Lung Lai ,  Hsien-Wei Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A method forming a redistribution line, which includes a via and a metal trace over and joined to the via, over a carrier. The formation of the redistribution line includes depositing a first metal layer, depositing a barrier layer over the first metal layer, and depositing a second metal layer over the barrier layer. The method further includes de-bonding the redistribution line from the carrier, and bonding a package component to the redistribution line, wherein a metal bump bonds the package component to the via.

公开(公告)号：US20230387028A1

公开(公告)日：2023-11-30

申请号：US18447769

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Yi-Wen Wu ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/4885 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

公开(公告)号：US20230343765A1

公开(公告)日：2023-10-26

申请号：US17804928

申请日：2022-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wei Chen ,  Meng-Liang Lin ,  Ying-Ju Chen ,  Shuo-Mao Chen

IPC: H01L25/10 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L25/105 ,  H01L25/50 ,  H01L23/5385 ,  H01L24/17 ,  H01L21/4857 ,  H01L25/18

Abstract: A method includes forming a first package component, which includes an interposer, and a first die bonded to a first side of the interposer. A second die is bonded to a second side of the interposer. The second die includes a substrate, and a through-via penetrating through the substrate. The method further includes bonding a second package component to the first package component through a first plurality of solder regions. The first package component is further electrically connected to the second package component through the through-via in the second die. The second die is further bonded to the second package component through a second plurality of solder regions.

公开(公告)号：US20220344317A1

公开(公告)日：2022-10-27

申请号：US17808621

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Meng-Wei Chou ,  Meng-Liang Lin

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

公开(公告)号：US11362010B2

公开(公告)日：2022-06-14

申请号：US16654187

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Liang Lin ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Yi-Wen Wu ,  Techi Wong ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/24 ,  H01L23/00 ,  H01L25/16 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L21/48

Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a semiconductor die over a first surface of a redistribution structure. The method also includes forming a first protective layer to surround a portion of the semiconductor die. The method further includes disposing a device element over a second surface of the redistribution structure. The redistribution structure is between the device element and the semiconductor die. In addition, the method includes forming a second protective layer to surround a portion of the device element. The second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different coefficients of thermal expansion.

公开(公告)号：US20210391317A1

公开(公告)日：2021-12-16

申请号：US16902017

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L21/56

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US20210035966A1

公开(公告)日：2021-02-04

申请号：US17068026

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Meng-Wei Chou ,  Meng-Liang Lin

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.