公开(公告)号：US20180173093A1

公开(公告)日：2018-06-21

申请号：US15380121

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng HSU ,  Hsin-Chang LEE ,  Yun-Yue LIN ,  Hsuan-Chen CHEN ,  Hsuan-I WANG ,  Anthony YEN

IPC: G03F1/64 ,  G03F1/22 ,  G03F7/20

CPC classification number: G03F1/64 ,  G03F1/22 ,  G03F7/2004

Abstract: A structure including an EUV mask and a pellicle attached to the EUV mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. The plurality of pellicle membrane layers include at least one core pellicle membrane layer and an additional pellicle membrane layer is disposed on the at least one core pellicle membrane layer. In some embodiments, the additional pellicle membrane layer is a material having a thermal emissivity greater than 0.2, a transmittance greater than 80%, and a refractive index (n) for 13.5 nanometer source of greater than 0.9.

公开(公告)号：US20150187663A1

公开(公告)日：2015-07-02

申请号：US14656754

申请日：2015-03-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hao HSU ,  Pei-Cheng HSU ,  Chia-Ching HUANG ,  Chih-Ming CHEN ,  Chia-Chen CHEN

IPC: H01L21/66 ,  G06F17/50 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

CPC classification number: H01L22/12 ,  G03F1/00 ,  G06F17/5068 ,  H01L21/02697 ,  H01L21/31144 ,  H01L21/32051 ,  H01L21/3212 ,  H01L21/32133

Abstract: A system and method of compensating for local focus errors in a semiconductor process. The method includes providing a reticle and applying, at a first portion of the reticle, a step height based on an estimated local focus error for a first portion of a wafer corresponding to the first portion of the reticle. A multilayer coating is formed over the reticle and an absorber layer is formed over the multilayer coating. A photoresist is formed over the absorber layer. The photoresist is patterned, an etch is performed of the absorber layer and residual photoresist is removed.

Abstract translation: 一种在半导体工艺中补偿局部焦点误差的系统和方法。 该方法包括提供掩模版并且在掩模版的第一部分处施加基于与掩模版的第一部分对应的晶片的第一部分的估计局部聚焦误差的台阶高度。 在掩模版上形成多层涂层，并在多层涂层上形成吸收层。 在吸收层上形成光致抗蚀剂。 对光致抗蚀剂进行图案化，对吸收层进行蚀刻并除去残留的光致抗蚀剂。

公开(公告)号：US20240192581A1

公开(公告)日：2024-06-13

申请号：US18395234

申请日：2023-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng HSU ,  Ta-Cheng LIEN ,  Hsin-Chang LEE

IPC: G03F1/24

CPC classification number: G03F1/24

Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a patterned absorber layer on the reflective multilayer stack is provided. The patterned absorber layer includes an alloy comprising tantalum and at least one alloying element. The at least one alloying element includes at least one transition metal element or at least one Group 14 element.

公开(公告)号：US20230375911A1

公开(公告)日：2023-11-23

申请号：US18365757

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Hsun LIN ,  Pei-Cheng HSU ,  Ching-Fang YU ,  Ta-Cheng LIEN ,  Chia-Jen CHEN ,  Hsin-Chang LEE

IPC: G03F1/24

CPC classification number: G03F1/24

Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.

公开(公告)号：US20230130162A1

公开(公告)日：2023-04-27

申请号：US17750145

申请日：2022-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hao LEE ,  Pei-Cheng HSU ,  Hsin-Chang LEE

IPC: C23C16/455 ,  H01J37/32

Abstract: A plasma enhanced atomic layer deposition (PEALD) system includes a process chamber. A target substrate is supported in the process chamber. A grid is positioned in the process chamber above the target substrate. The grid includes a plurality of apertures extending from a first side of the grid to a second side of the grid. During a PEALD process, a plasma generator generates a plasma. The energy of the plasma is reduced by passing the plasma through the apertures in the grid prior to reacting the plasma with the target substrate.

公开(公告)号：US20220082928A1

公开(公告)日：2022-03-17

申请号：US17532939

申请日：2021-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pei-Cheng HSU ,  Ta-Cheng LIEN ,  Hsin-Chang LEE

IPC: G03F1/24 ,  G03F1/22

Abstract: An extreme ultra-violet mask includes a substrate, a multi-layered mirror layer, a capping layer, a first tantalum-containing oxide layer, a tantalum-containing nitride layer, and a second tantalum-containing oxide layer. The multi-layered mirror layer is over the substrate. The capping layer is over the multi-layered mirror layer. The first tantalum-containing oxide layer is over the capping layer. The tantalum-containing nitride layer is over the first tantalum-containing oxide layer. The second tantalum-containing oxide layer is over the tantalum-containing nitride layer.

公开(公告)号：US20210364906A1

公开(公告)日：2021-11-25

申请号：US17065712

申请日：2020-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pei-Cheng HSU ,  Ta-Cheng LIEN ,  Hsin-Chang LEE

IPC: G03F1/24 ,  G03F1/54 ,  H01L21/027 ,  H01L21/033

Abstract: In a method of manufacturing a reflective mask, a photo resist layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a capping layer on the reflective multilayer, an absorber layer on the capping layer and a hard mask layer, and the absorber layer is made of Cr, CrO or CrON. The photo resist layer is patterned, the hard mask layer is patterned by using the patterned photo resist layer, the absorber layer is patterned by using the patterned hard mask layer, and an additional element is introduced into the patterned absorber layer to form a converted absorber layer.

公开(公告)号：US20200004133A1

公开(公告)日：2020-01-02

申请号：US16441700

申请日：2019-06-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pei-Cheng HSU ,  Chi-Ping WEN ,  Tzu Yi WANG ,  Ta-Cheng LIEN ,  Hsin-Chang LEE

IPC: G03F1/22

Abstract: A method of manufacturing an extreme ultraviolet (EUV) lithography mask includes forming an image pattern in an absorption layer of EUV mask blank. The EUV mask blank includes: a multilayer stack including alternating molybdenum (Mo) and silicon (Si) layers disposed over a first surface of a mask substrate, a capping layer disposed over the multilayer stack, and an absorption layer disposed over the capping layer. A border region surrounds the image pattern having a trench wherein the absorption layer, the capping layer and at least a portion of the multilayer stack are etched. Concave sidewalls are formed in the border region or an inter-diffused portion is formed in the multilayer stack of the trench.

公开(公告)号：US20250123552A1

公开(公告)日：2025-04-17

申请号：US18628337

申请日：2024-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng HSU ,  Hsuan-I WANG ,  Ping-Hsun LIN ,  Ching-Fang YU ,  Chia-Jen CHEN ,  Hsin-Chang LEE

IPC: G03F1/58 ,  G03F1/24 ,  G03F1/76 ,  G03F1/80 ,  G03F7/00

Abstract: An extreme ultraviolet (EUV) mask and method of forming an EUV mask are provided. The method includes forming a mask layer on a semiconductor wafer, generating extreme ultraviolet (EUV) light by a lithography exposure system, forming patterned EUV light by patterning the EUV light by a mask including an absorber having extinction coefficient at an EUV wavelength that exceeds extinction coefficients of TaBN and TaN at the EUV wavelength, and exposing the mask layer by the patterned EUV light.

公开(公告)号：US20240384410A1

公开(公告)日：2024-11-21

申请号：US18787915

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hao LEE ,  Pei-Cheng HSU ,  Hsin-Chang LEE

IPC: C23C16/455 ,  H01J37/32

Abstract: A plasma enhanced atomic layer deposition (PEALD) system includes a process chamber. A target substrate is supported in the process chamber. A grid is positioned in the process chamber above the target substrate. The grid includes a plurality of apertures extending from a first side of the grid to a second side of the grid. During a PEALD process, a plasma generator generates a plasma. The energy of the plasma is reduced by passing the plasma through the apertures in the grid prior to reacting the plasma with the target substrate.