公开(公告)号：US20160043188A1

公开(公告)日：2016-02-11

申请号：US14453304

申请日：2014-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Liang Chu ,  Chih-Wen Yao ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L29/417 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/6659 ,  H01L29/7833

Abstract: Some embodiments of the present disclosure relate to deceasing off-state leakage current within a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes source and drain regions. The source and drain regions are separated by a channel region. A gate is arranged over the channel region. The gate has a first gate region adjacent to the source region and a second gate region adjacent to the drain region. The first gate region is selectively doped adjacent the source region. The second gate region is undoped or lightly-doped. The undoped or lightly-doped second gate region reduces the electric field between the gate and the drain region, and hence reduces a gate induced drain leakage (GIDL) current between the gate and drain region. The undoped or lightly-doped region of the gate can reduce the GIDL current within the MOSFET by about three orders of magnitude. Other embodiments are also disclosed.

Abstract translation: 本公开的一些实施例涉及在金属氧化物半导体场效应晶体管（MOSFET）内去除截止状态的漏电流。 MOSFET包括源极和漏极区域。 源极和漏极区域被沟道区域分开。 在通道区域上设置一个门。 栅极具有与源极区域相邻的第一栅极区域和与漏极区域相邻的第二栅极区域。 第一栅极区域被选择性地掺杂在源极区附近。 第二栅极区域是未掺杂的或轻掺杂的。 未掺杂或轻掺杂的第二栅极区域减小栅极和漏极区域之间的电场，因此减小栅极和漏极区域之间的栅极感应漏极漏极（GIDL）电流。 栅极的未掺杂或轻掺杂区域可以将MOSFET内的GIDL电流降低约三个数量级。 还公开了其他实施例。

公开(公告)号：US12132108B2

公开(公告)日：2024-10-29

申请号：US17876795

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chih Su ,  Ruey-Hsin Liu ,  Pei-Lun Wang ,  Jia-Rui Lee ,  Jyun-Guan Jhou

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66659 ,  H01L29/7831

Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.

公开(公告)号：US20220223625A1

公开(公告)日：2022-07-14

申请号：US17323016

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L27/12 ,  H01L23/48 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.

公开(公告)号：US20200227528A1

公开(公告)日：2020-07-16

申请号：US16837401

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US20200013888A1

公开(公告)日：2020-01-09

申请号：US16026290

申请日：2018-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chih Su ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/765

Abstract: The present disclosure relates to a high voltage transistor device having a field structure that includes at least one conduction unit, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to over a drift region between the gate electrode and the drain region. A field structure is located within the first ILD layer. The field structure includes a conduction unit having a vertically elongated shape and vertically extending from a top surface of the dielectric layer and a top surface of the first ILD layer.

公开(公告)号：US09466715B2

公开(公告)日：2016-10-11

申请号：US14015350

申请日：2013-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/02

CPC classification number: H01L29/7833 ,  H01L21/0226 ,  H01L21/823462 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816

Abstract: A novel MOS transistor including a well region, a gate dielectric layer, a gate electrode, a source region and a drain region is provided. The well region of a first conductivity type extends into a semiconductor substrate. The gate dielectric layer is located over the well region. The gate electrode is located over the gate dielectric layer. The source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type are located in the well region and on opposite sides of the gate electrode. The gate dielectric layer has a first portion and a second portion respectively closest to the source region and the drain region. The thickness of the second portion is greater than that of the first portion, so as to raise breakdown voltage and to maintain current simultaneously.

Abstract translation: 提供了包括阱区，栅介质层，栅电极，源区和漏区的新型MOS晶体管。 第一导电类型的阱区延伸到半导体衬底中。 栅介质层位于阱区上方。 栅电极位于栅介电层上。 与第一导电类型相反的第二导电类型的源极区域和第二导电类型的漏极区域位于栅极电极的阱区域和相对侧。 栅极电介质层具有分别最靠近源极区域和漏极区域的第一部分和第二部分。 第二部分的厚度大于第一部分的厚度，以便提高击穿电压并同时维持电流。

公开(公告)号：US11088085B2

公开(公告)日：2021-08-10

申请号：US16924627

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC: H01L23/552 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L21/762

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

公开(公告)号：US20210057412A1

公开(公告)日：2021-02-25

申请号：US17088711

申请日：2020-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.

公开(公告)号：US10714432B1

公开(公告)日：2020-07-14

申请号：US16363114

申请日：2019-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC: H01L23/552 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L21/762

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

公开(公告)号：US20190237485A1

公开(公告)日：2019-08-01

申请号：US16382455

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Liang Chu ,  Chih-Wen Albert Yao ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L27/12 ,  H01L29/49 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/124 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/6659 ,  H01L29/7833

Abstract: Some embodiments of the present disclosure relate to a method of forming a transistor. The method includes forming a gate dielectric over a substrate and forming a gate over the gate dielectric. The gate includes polysilicon extending between a first outermost sidewall and a second outermost sidewall of the gate. A mask is formed over the gate. The mask exposes a first gate region extending to the first outermost sidewall and covers a second gate region extending between the first gate region and the second outermost sidewall. Dopants are selectively implanted into the first gate region according to the mask. Source and drain regions are formed within the substrate. The source region and the drain region are asymmetric with respect to an interface of the first gate region and the second gate region and extend to substantially equal distances past the first and second outermost sidewalls of the gate, respectively.