公开(公告)号：US20240371644A1

公开(公告)日：2024-11-07

申请号：US18778304

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.

公开(公告)号：US12019971B2

公开(公告)日：2024-06-25

申请号：US18183056

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin Chuang ,  Szu-ju Huang ,  Shih-Yao Lin ,  Shih Feng Hung ,  Yin-An Chen

IPC: G06F30/398 ,  G06F30/327 ,  G06F30/3315 ,  G06F30/394 ,  G06F30/396 ,  G06N5/04 ,  G06N20/00 ,  G06F119/12

CPC classification number: G06F30/398 ,  G06F30/327 ,  G06F30/394 ,  G06N5/04 ,  G06N20/00 ,  G06F30/3315 ,  G06F30/396 ,  G06F2119/12

Abstract: A violation prediction system includes machine learning circuitry trained based on past data to predict the presence of violations in electronic device designs after routing has been performed. The machine learning circuitry configured to predict, based on the past data and a pre-routing layout of an electronic device design, whether one or more violations would be present in in the electronic device design due to routing of the layout.

公开(公告)号：US11894277B2

公开(公告)日：2024-02-06

申请号：US17869590

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/823864 ,  H01L21/28123 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545

Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

公开(公告)号：US11837649B2

公开(公告)日：2023-12-05

申请号：US16939943

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785

Abstract: A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.

公开(公告)号：US11769821B2

公开(公告)日：2023-09-26

申请号：US17101291

申请日：2020-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Ping Chen ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.

公开(公告)号：US11715779B2

公开(公告)日：2023-08-01

申请号：US17682604

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Chung Chiu ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/66795 ,  H01L27/088

Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

公开(公告)号：US20220359709A1

公开(公告)日：2022-11-10

申请号：US17813839

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L29/78

Abstract: A method includes forming a dummy gate electrode on a semiconductor region, forming a first gate spacer on a sidewall of the dummy gate electrode, and removing an upper portion of the first gate spacer to form a recess, wherein a lower portion of the first gate spacer remains, filling the recess with a second gate spacer, removing the dummy gate electrode to form a trench, and forming a replacement gate electrode in the trench.

公开(公告)号：US11443096B2

公开(公告)日：2022-09-13

申请号：US17071862

申请日：2020-10-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC NANJING COMPANY LIMITED

Inventor： Yi-Lin Chuang ,  Shi-Wen Tan ,  Song Liu ,  Shih-Yao Lin ,  Wen-Yuan Fang

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/373 ,  G06F30/398 ,  G06F30/394

Abstract: A method is provided in the present disclosure. The method includes several operations: generating a floor plan having multiple macros for an integrated circuit; adjusting the macros according to a channel area interposed between the pins; separating the macros by a channel width of the channel area; and adjusting, in accordance with correlations between the macros and multiple registers, the macros in the floor plan.

公开(公告)号：US20220216322A1

公开(公告)日：2022-07-07

申请号：US17705804

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming are described herein. The methods include depositing a dummy gate material layer over a fin etched into a substrate. A gate mask is then formed over the dummy gate material layer in a channel region of the fin. A dummy gate electrode is etched into the dummy gate material using the gate mask. A top spacer is then deposited over the gate mask and along sidewalls of a top portion of the dummy gate electrode. An opening is then etched through the remainder of the dummy gate material and through the fin. A bottom spacer is then formed along a sidewall of the opening and separates a bottom portion of the dummy gate electrode from the opening. A source/drain region is then formed in the opening and the dummy gate electrode is replaced with a metal gate stack.

公开(公告)号：US20220173225A1

公开(公告)日：2022-06-02

申请号：US17650942

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.