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公开(公告)号：US10811263B2
公开(公告)日：2020-10-20
申请号：US16730343
申请日：2019-12-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Ya-Ling Lee , Shing-Chyang Pan , Keng-Chu Lin , Wen-Cheng Yang , Chih-Tsung Lee , Victor Y. Lu
IPC: H01L21/285 , H01L21/8234 , H01L21/3065 , H01L21/02 , H01L21/768
Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber and introducing a plasma-forming gas into the PVD chamber. The plasma-forming gas is an oxygen-containing gas. The method also includes applying a radio frequency (RF) power by a power source to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. The metal target is directly electrically coupled to the power source. The method further includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.
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公开(公告)号：US20200279770A1
公开(公告)日：2020-09-03
申请号：US16876965
申请日：2020-05-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Szu-Ping Tung , Jen Hung Wang , Shing-Chyang Pan
IPC: H01L21/768 , H01L23/532 , H01L23/522
Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.
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公开(公告)号：US10361112B2
公开(公告)日：2019-07-23
申请号：US15725996
申请日：2017-10-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wan-Lin Tsai , Shing-Chyang Pan , Sung-En Lin , Tze-Liang Lee , Jung-Hau Shiu , Jen Hung Wang
IPC: H01L29/66 , H01L29/49 , H01L21/8234 , H01L27/088 , H01L21/768 , H01L21/762 , H01L21/02
Abstract: The present disclosure describes a method of forming a dielectric layer or a dielectric stack on a photoresist layer while minimizing or avoiding damage to the photoresist. In addition, the dielectric layer or dielectric stack can till high-aspect ratio openings and can be removed with etching. The dielectric layer or dielectric stack can be deposited with a conformal, low-temperature chemical vapor deposition process or a conformal, low-temperature atomic layer deposition process that utilizes a number of precursors and plasmas or reactant gases.
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公开(公告)号：US20180350666A1
公开(公告)日：2018-12-06
申请号：US16043343
申请日：2018-07-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Szu-Ping Tung , Jen Hung Wang , Shing-Chyang Pan
IPC: H01L21/768 , H01L23/532 , H01L23/522
CPC classification number: H01L21/76829 , H01L21/76802 , H01L21/7682 , H01L21/76843 , H01L21/76877 , H01L23/5222 , H01L23/5226 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L23/53295
Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.
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公开(公告)号：US12074058B2
公开(公告)日：2024-08-27
申请号：US18308937
申请日：2023-04-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Ren Wang , Shing-Chyang Pan , Ching-Yu Chang , Wan-Lin Tsai , Jung-Hau Shiu , Tze-Liang Lee
IPC: H01L21/76 , H01L21/02 , H01L21/033 , H01L21/311 , H01L21/768
CPC classification number: H01L21/76802 , H01L21/02167 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/0337 , H01L21/31144 , H01L21/76879
Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.
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Patent Agency Ranking
公开(公告)号：US20230260829A1
公开(公告)日：2023-08-17
申请号：US18308937
申请日：2023-04-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Ren Wang , Shing-Chyang Pan , Ching-Yu Chang , Wan-Lin Tsai , Jung-Hau Shiu , Tze-Liang Lee
IPC: H01L21/768 , H01L21/311 , H01L21/02 , H01L21/033
CPC classification number: H01L21/76802 , H01L21/76879 , H01L21/31144 , H01L21/02167 , H01L21/0228 , H01L21/02274 , H01L21/02211 , H01L21/0337
Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.
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公开(公告)号：US11479849B2
公开(公告)日：2022-10-25
申请号：US16429187
申请日：2019-06-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hai-Dang Trinh , Chii-Ming Wu , Shing-Chyang Pan
Abstract: A sputtering system includes a vacuum chamber, a power source having a pole coupled to a backing plate for holding a sputtering target within the vacuum chamber, a pedestal for holding a substrate within the vacuum chamber, and a time of flight camera positioned to scan a surface of a target held to the backing plate. The time of flight camera may be used to obtain information relating to the topography of the target while the target is at sub-atmospheric pressure. The target information may be used to manage operation of the sputtering system. Managing operation of the sputtering system may include setting an adjustable parameter of a deposition process or deciding when to replace a sputtering target. Machine learning may be used to apply the time of flight camera data in managing the sputtering system operation.
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28.发明授权公开(公告)号：US11040870B2
公开(公告)日：2021-06-22
申请号：US16521907
申请日：2019-07-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Kuei-Sung Chang , Chun-Wen Cheng , Fei-Lung Lai , Shing-Chyang Pan , Yuan-Chih Hsieh , Yi-Ren Wang
Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.
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29.发明申请公开(公告)号：US20210087055A1
公开(公告)日：2021-03-25
申请号：US16579713
申请日：2019-09-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Ren Wang , Shing-Chyang Pan , Yuan-Chih Hsieh
Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capping structure over a device substrate. The device substrate includes a first microelectromechanical systems (MEMS) device and a second MEMS device laterally offset from the first MEMS device. The capping structure includes a first cavity overlying the first MEMS device and a second cavity overlying the second MEMS device. The first cavity has a first gas pressure and the second cavity has a second gas pressure different from the first cavity. An outgas layer abutting the first cavity. The outgas layer includes an outgas material having an outgas species. The outgas material is amorphous.
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公开(公告)号：US20200377997A1
公开(公告)日：2020-12-03
申请号：US16429187
申请日：2019-06-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hai-Dang Trinh , Chii-Ming Wu , Shing-Chyang Pan
Abstract: A sputtering system includes a vacuum chamber, a power source having a pole coupled to a backing plate for holding a sputtering target within the vacuum chamber, a pedestal for holding a substrate within the vacuum chamber, and a time of flight camera positioned to scan a surface of a target held to the backing plate. The time of flight camera may be used to obtain information relating to the topography of the target while the target is at sub-atmospheric pressure. The target information may be used to manage operation of the sputtering system. Managing operation of the sputtering system may include setting an adjustable parameter of a deposition process or deciding when to replace a sputtering target. Machine learning may be used to apply the time of flight camera data in managing the sputtering system operation.
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