公开(公告)号：US11495687B2

公开(公告)日：2022-11-08

申请号：US17001390

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Chih-Ming Lai ,  Ching-Wei Tsai ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kuo-Cheng Chiang ,  Ru-Gun Liu ,  Wei-Hao Wu ,  Yi-Hsiung Lin ,  Chia-Hao Chang ,  Lei-Chun Chou

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66 ,  H01L23/485 ,  H01L21/74 ,  H01L23/538 ,  H01L23/535 ,  H01L29/417

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US11127631B2

公开(公告)日：2021-09-21

申请号：US16149597

申请日：2018-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L23/528 ,  H01L23/535 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/768

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a first conductive via electrically connected to the first epitaxial structure through a conductive contact. The first conductive via is misaligned with the first epitaxial structure. The semiconductor device structure further includes a second conductive via electrically connected to the second epitaxial structure. The second conductive via is aligned with the second epitaxial structure.

公开(公告)号：US11063041B2

公开(公告)日：2021-07-13

申请号：US16583438

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/50

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

公开(公告)号：US10818473B2

公开(公告)日：2020-10-27

申请号：US16539513

申请日：2019-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Cheng-En Lee ,  Chia-Lin Ou ,  Hsuan-Pang Liu ,  Yao-Jen Yeh

IPC: H01J37/08 ,  H01J37/31 ,  H01J37/317 ,  H01J37/30

Abstract: The present disclosure relates to a method includes generating ions with an ion source of an ion implantation apparatus based on an ion implantation recipe. The method includes accelerating the generated ions based on an ion energy setting in the ion implantation recipe and determining an energy spectrum of the accelerated ions. The method also includes analyzing a relationship between the determined energy spectrum and the ion energy setting. The method further includes adjusting at least one parameter of a final energy magnet (FEM) of the ion implantation apparatus based on the analyzed relationship.

公开(公告)号：US10763365B2

公开(公告)日：2020-09-01

申请号：US16176072

申请日：2018-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Chih-Ming Lai ,  Ching-Wei Tsai ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kuo-Cheng Ching ,  Ru-Gun Liu ,  Wei-Hao Wu ,  Yi-Hsiung Lin ,  Chia-Hao Chang ,  Lei-Chun Chou

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66 ,  H01L23/535 ,  H01L21/8234 ,  H01L23/48 ,  H01L29/417

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20200111702A1

公开(公告)日：2020-04-09

申请号：US16704195

申请日：2019-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ethan Hsiao ,  Chien Wen Lai ,  Chih-Ming Lai ,  Yi-Hsiung Lin ,  Cheng-Chi Chuang ,  Hsin-Ping Chen ,  Ru-Gun Liu

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/8234

Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.

公开(公告)号：US20240371868A1

公开(公告)日：2024-11-07

申请号：US18774323

申请日：2024-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Guo-Huei Wu ,  Yu-Jung Chang

IPC: H01L27/088 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H10B12/00

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US12113132B2

公开(公告)日：2024-10-08

申请号：US18053021

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Chih-Ming Lai ,  Ching-Wei Tsai ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kuo-Cheng Chiang ,  Ru-Gun Liu ,  Wei-Hao Wu ,  Yi-Hsiung Lin ,  Chia-Hao Chang ,  Lei-Chun Chou

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/485 ,  H01L23/50 ,  H01L23/528 ,  H01L23/535 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/76871 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/41791

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US11682590B2

公开(公告)日：2023-06-20

申请号：US17391271

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L21/823871 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/6681 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, a first epitaxial source/drain (S/D) feature disposed over the first semiconductor fin, a second epitaxial S/D feature disposed over the second semiconductor fin, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and an S/D contact disposed over and contacting the first epitaxial S/D feature, where a portion of the S/D contact laterally extends over the second epitaxial S/D feature, and the portion is separated from the second epitaxial S/D feature by the ILD layer.

公开(公告)号：US11437385B2

公开(公告)日：2022-09-06

申请号：US16526415

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Wang ,  Yi-Hsun Chiu ,  Yi-Hsiung Lin ,  Shang-Wen Chang

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/417 ,  H01L21/762 ,  H01L29/423 ,  G11C11/412

Abstract: A static random access memory (SRAM) cell includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The SRAM cell further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.