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    Semiconductor device including anti-fuse cell
    21.
    发明授权
    Semiconductor device including anti-fuse cell 有权

    公开(公告)号：US11600626B2

    公开(公告)日：2023-03-07

    申请号：US16713967

    申请日：2019-12-13

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Meng-Sheng Chang ,  Yao-Jen Yang ,  Yih Wang ,  Fu-An Wu

    IPC: H01L27/112 ,  G11C7/10 ,  H01L23/522 ,  G11C17/16 ,  H01L23/525 ,  G11C5/06 ,  G11C8/08 ,  G11C17/18

    Abstract: A structure includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

    Memory device and manufacturing method thereof
    22.
    发明授权
    Memory device and manufacturing method thereof 有权

    公开(公告)号：US11315936B2

    公开(公告)日：2022-04-26

    申请号：US16805868

    申请日：2020-03-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Hsun Chiu ,  Yih Wang

    IPC: H01L29/66 ,  H01L21/84 ,  H01L27/112 ,  H01L23/525

    Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a transistor, a first embedded insulating structure and a second embedded insulating structure. The transistor is formed on a substrate, and includes a gate structure, channel structures, a source electrode and a drain electrode. The channel structures penetrate through the gate structure, and are in contact with the source and drain electrodes. The first and second embedded insulating structures are disposed in the substrate, and overlapped with the source and drain electrodes. The first and second embedded insulating structures are laterally spaced apart from each other by a portion of the substrate lying under the gate structure.

    Memory Array Word Line Routing
    24.
    发明申请
    Memory Array Word Line Routing 有权

    公开(公告)号：US20210398568A1

    公开(公告)日：2021-12-23

    申请号：US17015679

    申请日：2020-09-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Chenchen Jacob Wang ,  Yi-Ching Liu ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Yih Wang

    IPC: G11C5/06 ,  H01L27/11587 ,  H01L29/24 ,  H01L27/11597 ,  H01L29/78

    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material contacting a first word line; an oxide semiconductor (OS) layer contacting a source line and a bit line, the FE material being disposed between the OS layer and the first word line; a dielectric material contacting the FE material, the FE material being between the dielectric material and the first word line; an inter-metal dielectric (IMD) over the first word line; a first contact extending through the IMD to the first word line, the first contact being electrically coupled to the first word line; a second contact extending through the dielectric material and the FE material; and a first conductive line electrically coupling the first contact to the second contact.

    TEST DEVICE FOR MEMORY, METHOD FOR DETECTING HARDWARE FAILURE IN MEMORY DEVICE, AND TEST APPARATUS OF MEMORY ARRAY
    25.
    发明申请
    TEST DEVICE FOR MEMORY, METHOD FOR DETECTING HARDWARE FAILURE IN MEMORY DEVICE, AND TEST APPARATUS OF MEMORY ARRAY 有权

    公开(公告)号：US20210312999A1

    公开(公告)日：2021-10-07

    申请号：US16836928

    申请日：2020-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

    IPC: G11C29/38 ,  G11C29/36

    Abstract: A testing device for memory includes a memory array and a test apparatus. The test apparatus includes a controller and a pattern generator. The pattern generator generates a background data, a first pattern data, and a second pattern data. The controller sets up the background data to a to-be-tested memory sub-array of the memory sub-arrays, performs a first memory test operation with the to-be-tested memory sub-array according to the first pattern data for detecting whether the hardware failure of the to-be-tested memory sub-array is occurred during the first memory test operation. The controller performs a second memory test operation with the to-be-tested memory sub-array according to the second pattern data for detecting whether the hardware failure of the to-be-tested memory sub-array is occurred during the second memory test operation in response to the hardware failure of the to-be-tested memory sub-array is not occurred during the first memory test operation.

    LAYOUT STRUCTURE INCLUDING ANTI-FUSE CELL
    26.
    发明申请
    LAYOUT STRUCTURE INCLUDING ANTI-FUSE CELL 有权

    公开(公告)号：US20210202503A1

    公开(公告)日：2021-07-01

    申请号：US16729973

    申请日：2019-12-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Wan-Hsueh Cheng ,  Yao-Jen Yang ,  Yih Wang

    IPC: H01L27/112 ,  H01L23/528 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  G06F30/392

    Abstract: A structure includes a first data line and a first anti-fuse cell including first/second programming devices and first/second reading devices. The first programming device includes a first gate and first/second source/drain regions disposing on opposite sides of first gate. The second programming device includes a second gate separate from the first gate and coupled to a first word line and third/fourth source/drain regions disposing on opposite sides of second gate. The first reading device includes a third gate and fifth/sixth source/drain regions disposing on opposite sides of third gate. The second reading device includes a fourth gate and seventh/eighth source/drain regions disposing on opposite sides of fourth gate. The third/fourth gates are parts of the first continuous gate coupled to a second word line. The fifth/seventh source/drain regions are coupled to the second/fourth source/drain regions, respectively. The sixth/eighth source/drain regions are coupled to the first data line.

    Method and system for refresh of memory devices
    28.
    发明授权
    Method and system for refresh of memory devices 有权

    公开(公告)号：US11810611B2

    公开(公告)日：2023-11-07

    申请号：US17716446

    申请日：2022-04-08

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hiroki Noguchi ,  Yih Wang

    IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/4076

    CPC classification number: G11C11/40611 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/40626

    Abstract: A memory system is provided. The memory system includes a controller configured to refresh a memory array at a first temperature before a first refresh time that is acquired from a lookup table and corresponds to a time period for stored data in the memory array being lost at the first temperature. After the controller acquires a second refresh time from the lookup table, the controller resets a refresh time period to refresh the memory array before the second refresh time. The second refresh time corresponds to a time period for stored data in the memory array being lost at a second temperature different from the first temperature. The refresh time period corresponds to a time period after refreshing the memory array.

    Current steering in reading magnetic tunnel junction
    29.
    发明授权
    Current steering in reading magnetic tunnel junction 有权

    公开(公告)号：US11676648B2

    公开(公告)日：2023-06-13

    申请号：US17703869

    申请日：2022-03-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  Yih Wang

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C11/161

    Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.

    Method of minimizing read-disturb-write effect of SRAM circuit and SRAM circuit thereof
    30.
    发明授权
    Method of minimizing read-disturb-write effect of SRAM circuit and SRAM circuit thereof 有权

    公开(公告)号：US11200924B2

    公开(公告)日：2021-12-14

    申请号：US16876138

    申请日：2020-05-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jui-Che Tsai ,  Chia-En Huang ,  Yu-Hao Hsu ,  Yih Wang

    IPC: G11C7/10 ,  G11C7/12 ,  G11C7/06

    Abstract: In an exemplary embodiment, the disclosure provides a memory circuit which includes a dual port memory cell for storing a binary value accessed through a first port and a second port, a first WL switch connected to the dual port memory cell and controlled by a first WL voltage, a second WL switch connected to the dual port memory cell and controlled by a second WL voltage, a BL connected to the first WL switch for accessing the memory cell through the first port and having a first BL voltage, a second BL connected to the second WL switch for accessing the memory cell through the second port and having a second BL voltage, a BL selection circuit connected to the second WL switch for selecting the second BL, and a BL voltage pull down circuit connected to the BL selection circuit and the second WL switch.

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