公开(公告)号：US11257924B2

公开(公告)日：2022-02-22

申请号：US16746097

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

公开(公告)号：US11189714B2

公开(公告)日：2021-11-30

申请号：US16928423

申请日：2020-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chi Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/3115 ,  H01L21/311 ,  H01L29/49 ,  H01L29/08 ,  H01L29/165 ,  H01L29/51

Abstract: Embodiments of the present disclosure provide a method of cleaning a lanthanum containing substrate without formation of undesired lanthanum compounds during processing. In one embodiment, the cleaning method includes treating the lanthanum containing substrate with an acidic solution prior to cleaning the lanthanum containing substrate with a HF solution. The cleaning method permits using lanthanum doped high-k dielectric layer to modulate effective work function of the gate stack, thus, improving device performance.

公开(公告)号：US20210193469A1

公开(公告)日：2021-06-24

申请号：US17187176

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/28 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/3213

Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.

公开(公告)号：US11031302B2

公开(公告)日：2021-06-08

申请号：US16517767

申请日：2019-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Chih-Long Chiang ,  Kuo Bin Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang

IPC: H01L21/8238 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/49

Abstract: Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid.

公开(公告)号：US10283503B2

公开(公告)日：2019-05-07

申请号：US15799555

申请日：2017-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chi Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423

Abstract: Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.

公开(公告)号：US12255107B2

公开(公告)日：2025-03-18

申请号：US18410589

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Hsu ,  Ming-Chi Huang ,  Ying-Liang Chuang

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/3213

Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.

公开(公告)号：US20240096707A1

公开(公告)日：2024-03-21

申请号：US18521140

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chi Huang ,  Kuo-Bin Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854 ,  H01L27/0924

Abstract: A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.

公开(公告)号：US20230378360A1

公开(公告)日：2023-11-23

申请号：US18361514

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Hsin-Che Chiang ,  Yu-Chi Pan ,  Chun-Ming Yang ,  Chun-Sheng Liang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/285 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/49

CPC classification number: H01L29/785 ,  H01L29/42372 ,  H01L21/28556 ,  H01L29/401 ,  H01L21/32134 ,  H01L29/4966

Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

公开(公告)号：US20220319933A1

公开(公告)日：2022-10-06

申请号：US17838495

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Hsu ,  Ming-Chi Huang ,  Ying-Liang Chuang

IPC: H01L21/8238 ,  H01L21/3213 ,  H01L21/28

Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.

公开(公告)号：US20200152772A1

公开(公告)日：2020-05-14

申请号：US16746097

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/78

Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.