公开(公告)号：US20210376163A1

公开(公告)日：2021-12-02

申请号：US17206646

申请日：2021-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Zhiqiang Wu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

公开(公告)号：US20210296485A1

公开(公告)日：2021-09-23

申请号：US17341142

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzer-Min Shen ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H01L29/78 ,  H01L29/10

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.

公开(公告)号：US20210090631A1

公开(公告)日：2021-03-25

申请号：US17110624

申请日：2020-12-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu

IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a first read bias transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first read bias transistor. The first non-linear resistance device is configured to provide a first resistance when applied a first voltage and a second resistance greater than the first resistance when applied a second voltage smaller than the first voltage.

公开(公告)号：US20200321461A1

公开(公告)日：2020-10-08

申请号：US16909079

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Ka-Hing Fung ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

公开(公告)号：US09768297B2

公开(公告)日：2017-09-19

申请号：US14935760

申请日：2015-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Chia-Wen Liu ,  Yeh Hsu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L21/02 ,  H01L29/08 ,  H01L29/16 ,  H01L29/10 ,  H01L29/161

CPC classification number: H01L29/7836 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.

公开(公告)号：US09653545B2

公开(公告)日：2017-05-16

申请号：US14661237

申请日：2015-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mahaveer Sathaiya Dhanyakumar ,  Wei-Hao Wu ,  Tsung-Hsing Yu ,  Chia-Wen Liu ,  Tzer-Min Shen ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/265

CPC classification number: H01L29/0653 ,  H01L21/26586 ,  H01L21/76232 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

公开(公告)号：US09455346B2

公开(公告)日：2016-09-27

申请号：US14100263

申请日：2013-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

Abstract translation: IC的性能提升和几何尺寸的需求引起了包括finFET器件在内的多栅极器件的引入。 在区域中诱导更高的拉伸应变/应力提供增强的电子迁移率，这可以提高性能。 器件制造期间的高温工艺往往会使这些应变诱导层的应力松弛。 本公开涉及在finFET器件形成工艺的RPG（替代多晶硅栅极）级形成应变诱导层或覆盖层的方法。 在一些实施例中，应变诱导层被掺杂以减小外部电阻。

公开(公告)号：US20150200272A1

公开(公告)日：2015-07-16

申请号：US14156505

申请日：2014-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Wen Liu ,  Tsung-Hsing Yu ,  Wei-Hao Wu ,  Meikei Ieong ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/36

CPC classification number: H01L29/66545 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: The disclosure provides a method of forming a transistor. In this method, a dummy gate structure is formed over a semiconductor substrate. Source/drain regions are then formed in the semiconductor substrate such that a channel region, which is arranged under the dummy gate structure in the semiconductor substrate, separates the source/drains from one another. After the source/drain regions have been formed, the dummy gate structure is removed. After the dummy gate structure has been removed, a surface region of the channel region is removed to form a channel region recess. A replacement channel region is then epitaxially grown in the channel region recess.

Abstract translation: 本公开提供了一种形成晶体管的方法。 在该方法中，在半导体衬底上形成虚拟栅极结构。 然后在半导体衬底中形成源极/漏极区，使得布置在半导体衬底中的伪栅极结构下方的沟道区彼此分离源极/漏极。 在形成源极/漏极区之后，去除伪栅极结构。 在虚拟栅极结构被去除之后，去除沟道区域的表面区域以形成沟道区域凹陷。 然后在沟道区域凹陷中外延生长替换沟道区。

公开(公告)号：US20150028426A1

公开(公告)日：2015-01-29

申请号：US13952753

申请日：2013-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Zhiqiang Wu ,  Gwan Sin Chang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7849

Abstract: The present disclosure relates to a Fin field effect transistor (FinFET) device having a buried silicon germanium oxide structure configured to enhance performance of the FinFET device. In some embodiments, the FinFET device has a three-dimensional fin of semiconductor material protruding from a substrate at a position located between first and second isolation regions. A gate structure overlies the three-dimensional fin of semiconductor material. The gate structure controls the flow of charge carriers within the three-dimensional fin of semiconductor material. A buried silicon-germanium-oxide (SiGeOx) structure is disposed within the three-dimensional fin of semiconductor material at a position extending between the first and second isolation regions.

Abstract translation: 本公开涉及具有被配置为增强FinFET器件的性能的掩埋硅锗氧化物结构的Fin场效应晶体管（FinFET）器件。 在一些实施例中，FinFET器件具有在位于第一和第二隔离区域之间的位置处从衬底突出的半导体材料的三维鳍。 栅极结构覆盖半导体材料的三维鳍。 栅极结构控制半导体材料的三维鳍内的电荷载流子的流动。 掩埋的硅 - 锗氧化物（SiGeOx）结构设置在半导体材料的三维翅片内，在第一和第二隔离区域之间延伸的位置。

公开(公告)号：US12300749B2

公开(公告)日：2025-05-13

申请号：US18447483

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Wen-Yuan Chen ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.