公开(公告)号：US12300749B2

公开(公告)日：2025-05-13

申请号：US18447483

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Wen-Yuan Chen ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

公开(公告)号：US20240258407A1

公开(公告)日：2024-08-01

申请号：US18623143

申请日：2024-04-01

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Chih-Ching Wang ,  Chung-I Yang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/785 ,  H01L2029/7858

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members vertically stacked above a substrate, a gate structure engaging the channel members, a gate sidewall spacer disposed on a sidewall of the gate structure, an epitaxial feature abutting end portions of the channel members, and inner spacers interposing the gate structure and the epitaxial feature. The end portion of at least one of the channel members includes a first dopant. A concentration of the first dopant in the end portion of the at least one of the channel members is higher than in a center portion of the at least one of the channel members. The concentration of the first dopant in the end portion of the at least one of the channel members is higher than in an outer portion of the epitaxial feature.

公开(公告)号：US20220359752A1

公开(公告)日：2022-11-10

申请号：US17314815

申请日：2021-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Wen-Yuan Chen ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/265 ,  H01L29/66

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

公开(公告)号：US20210066490A1

公开(公告)日：2021-03-04

申请号：US16559343

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Han-Yu Lin ,  Chun-Yu Chen ,  Chih-Ching Wang ,  Fang-Wei Lee ,  Tze-Chung LIN ,  Li-Te LIN ,  Gwan-Sin Chang ,  Pinyen LIN

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66

Abstract: The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.

公开(公告)号：US09373620B2

公开(公告)日：2016-06-21

申请号：US14485541

申请日：2014-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Chi Wang ,  Chien-Chih Lee ,  Tien-Wei Chiang ,  Ching-Wei Tsai ,  Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh

IPC: H01L29/66 ,  H01L21/336 ,  H01L27/088 ,  H01L29/78 ,  H01L29/45 ,  H01L29/06 ,  H01L23/528 ,  H01L21/283 ,  H01L21/306 ,  H01L21/768 ,  H01L21/31

CPC classification number: H01L27/088 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/76897 ,  H01L21/823487 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.

Abstract translation: 串联连接的晶体管结构包括第一源极，第一沟道 - 漏极结构，第二沟道 - 漏极结构，栅极电介质层，栅极，第一漏极焊盘和第二漏极焊盘。 第一个来源是在一个基板上。 第一沟道 - 漏极结构在第一源极上并且包括第一沟道和第一漏极。 第二沟道 - 漏极结构在第一源极上并且基本上平行于第一沟道 - 漏极结构并且包括第二沟道和第二漏极。 栅介质层围绕第一通道和第二通道。 栅极围绕栅介质层。 第一个漏极焊盘是与第一个漏极接触的。 第二漏极焊盘与第二漏极接触，其中第一漏极焊盘和第二漏极焊盘彼此分离。

公开(公告)号：US08981479B2

公开(公告)日：2015-03-17

申请号：US14108391

申请日：2013-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Jon-Hsu Ho ,  Ching-Fang Huang ,  Wen-Hsing Hsieh ,  Tsung-Hsing Yu ,  Yi-Ming Sheu ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.

Abstract translation: 一种多栅半导体器件及其制造方法。 形成多栅半导体器件，其包括形成在具有第一掺杂剂类型的半导体衬底上的第一晶体管的第一鳍。 第一晶体管具有第一掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一掺杂剂型半导体衬底上的第二晶体管的第二鳍。 第二晶体管具有第二掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一鳍片的沟道区域上的第二掺杂剂类型的栅极电极层和形成在第二鳍片的沟道区域上的第一掺杂剂类型的栅极电极层。