公开(公告)号：US10861972B2

公开(公告)日：2020-12-08

申请号：US16390373

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. In some embodiments, the present disclosure relates to a finFET device and its formation. A strain-inducing layer is disposed on a semiconductor fin between a channel region and a metal gate electrode. First and second inner spacers are disposed on a top surface of the strain-inducing layer and have inner sidewalls disposed along outer sidewalls of the metal gate electrode. First and second outer spacers have innermost sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively. The first and second outer spacers cover outer sidewalls of the first and second inner spacers.

公开(公告)号：US20250151305A1

公开(公告)日：2025-05-08

申请号：US19018623

申请日：2025-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju Lee ,  Zhiqiang Wu ,  Chung-Wei Wu ,  Chun-Fu Cheng

IPC: H10D30/01 ,  H01L21/02 ,  H10D30/62 ,  H10D30/67 ,  H10D62/00 ,  H10D62/10 ,  H10D62/13 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83

Abstract: The present disclosure provides a semiconductor device that includes channel layers vertically stacked over a substrate, a gate structure engaging the channel layers, a source/drain (S/D) formation assistance region partially embedded in the substrate and under a bottommost one of the channel layers, and an S/D epitaxial feature interfacing both the S/D formation assistance region and lateral ends of the channel layers. The S/D formation assistance region includes a semiconductor seed layer embedded in an isolation layer. The isolation layer separates the semiconductor seed layer from physically contacting the substrate.

公开(公告)号：US12199170B2

公开(公告)日：2025-01-14

申请号：US18066373

申请日：2022-12-15

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a stack of first semiconductor layers and second semiconductor layers over a substrate, etching the stack to form a source/drain (S/D) recess in exposing the substrate, and forming an S/D formation assistance region in the S/D recess. The S/D formation assistance region is partially embedded in the substrate and includes a semiconductor seed layer embedded in an isolation layer. The isolation layer electrically isolates the semiconductor seed layer from the substrate. The method also includes epitaxially growing an S/D feature in the S/D recess from the semiconductor seed layer. The S/D feature is in physical contact with the second semiconductor layers.

公开(公告)号：US12040222B2

公开(公告)日：2024-07-16

申请号：US17682234

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Yu Lin ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76802 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76897

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.

公开(公告)号：US20240072115A1

公开(公告)日：2024-02-29

申请号：US18168504

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Xiang You ,  Wei-De Ho ,  Hsin Yang Hung ,  Meng-Yu Lin ,  Hsiang-Hung Huang ,  Chun-Fu Cheng ,  Kuan-Kan Hu ,  Szu-Hua Chen ,  Ting-Yun Wu ,  Wei-Cheng Tzeng ,  Wei-Cheng Lin ,  Cheng-Yin Wang ,  Jui-Chien Huang ,  Szuya Liao

IPC: H01L29/06 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/5283 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78696

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact. The interconnect structure includes: a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being in the gate isolation structure; an opening in the conductive layer, the opening overlapping the fourth source/drain region, the second source/drain region or both; and a dielectric layer in the opening and on the conductive layer in the gate isolation structure.

公开(公告)号：US11837538B2

公开(公告)日：2023-12-05

申请号：US17723116

申请日：2022-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Wei Ju Lee ,  Cheng-Ting Chung ,  Hou-Yu Chen ,  Chun-Fu Cheng ,  Kuan-Lun Cheng

IPC: H01L23/522 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

公开(公告)号：US11469332B2

公开(公告)日：2022-10-11

申请号：US16667615

申请日：2019-10-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a substrate, a plurality of nanowires, a gate structure, a source/drain epitaxy structure, and a semiconductor layer. The substrate has a protrusion portion. The nanowires extend in a first direction above the protrusion portion of the substrate, the nanowires being arranged in a second direction substantially perpendicular to the first direction. The gate structure wraps around each of the nanowires. The source/drain epitaxy structure is in contact with an end surface of each of the nanowires, in which a bottom surface of the source/drain epitaxy structure is lower than a top surface of the protrusion portion of the substrate. The semiconductor layer is in contact with the bottom surface of the epitaxy structure, in which the semiconductor layer is spaced from the protrusion portion of the substrate.

公开(公告)号：US11309240B2

公开(公告)日：2022-04-19

申请号：US16832833

申请日：2020-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Wei Ju Lee ,  Cheng-Ting Chung ,  Hou-Yu Chen ,  Chun-Fu Cheng ,  Kuan-Lun Cheng

IPC: H01L23/522 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

公开(公告)号：US10516047B2

公开(公告)日：2019-12-24

申请号：US15471318

申请日：2017-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou Sio ,  Jiann-Tyng Tzeng ,  Charles Chew-Yuen Young ,  Yi-Ming Sheu ,  Chun-Fu Cheng ,  Yi-Han Wang

IPC: H01L29/775 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/417 ,  H01L29/423

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer. The semiconductor device structure also includes a gate stack structure in the dielectric layer. The semiconductor device structure further includes a semiconductor wire partially surrounded by the gate stack structure. In addition, the semiconductor device structure includes a contact electrode in the dielectric layer and electrically connected to the semiconductor wire. The contact electrode and the gate stack structure extend from the semiconductor wire in opposite directions.

公开(公告)号：US20190245089A1

公开(公告)日：2019-08-08

申请号：US16390373

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. In some embodiments, the present disclosure relates to a finFET device and its formation. A strain-inducing layer is disposed on a semiconductor fin between a channel region and a metal gate electrode. First and second inner spacers are disposed on a top surface of the strain-inducing layer and have inner sidewalls disposed along outer sidewalls of the metal gate electrode. First and second outer spacers have innermost sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively. The first and second outer spacers cover outer sidewalls of the first and second inner spacers.