公开(公告)号：US20220359193A1

公开(公告)日：2022-11-10

申请号：US17814716

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Chung-Chiang Wu ,  Shih-Hang Chiu ,  Hsuan-Yu Tung ,  Da-Yuan Lee

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66

Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

公开(公告)号：US20220336285A1

公开(公告)日：2022-10-20

申请号：US17809944

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Han Tsai ,  Chung-Chiang Wu ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.

公开(公告)号：US11387344B2

公开(公告)日：2022-07-12

申请号：US16889217

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hung-Chin Chung ,  Chung-Chiang Wu ,  Hsuan-Yu Tung ,  Kuan-Chang Chiu ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

公开(公告)号：US11322411B2

公开(公告)日：2022-05-03

申请号：US16686408

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen Tsai ,  Chung-Chiang Wu ,  Tai-Wei Hwang ,  Hung-Chin Chung ,  Wei-Chin Lee ,  Da-Yuan Lee ,  Ching-Hwanq Su ,  Yin-Chuan Chuang ,  Kuan-Ting Liu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L29/51

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

公开(公告)号：US10741400B2

公开(公告)日：2020-08-11

申请号：US16173857

申请日：2018-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh Wen Tsau ,  Chia-Ching Lee ,  Chung-Chiang Wu ,  Da-Yuan Lee

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L29/78

Abstract: A semiconductor device structure is provided. The semiconductor device includes a plurality of fins on a substrate, and a metal gate structure disposed on the plurality of fins. The metal gate structure includes a work function metal layer over the plurality of fins, a metal layer on the work function metal layer, and a metal oxide layer on the metal layer. A first portion of the metal oxide layer is formed within an area between adjacent fins from among the plurality of tins. An example benefit includes reduced diffusion of unwanted and/or detrimental elements from the first metal layer into its underlying layers and consequently, the reduction of the negative impact of these unwanted and/or detrimental elements on the semiconductor device performance.

公开(公告)号：US09824969B1

公开(公告)日：2017-11-21

申请号：US15154989

申请日：2016-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Chiang Wu ,  Chia-Ching Lee ,  Hsueh-Wen Tsau ,  Chun-Yuan Chou ,  Cheng-Yen Tsai ,  Da-Yuan Lee ,  Ming-Hsing Tsai

IPC: H01L23/52 ,  H01L21/4763 ,  H01L21/44 ,  H01L29/66 ,  H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L29/49

CPC classification number: H01L23/528 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76861 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53261 ,  H01L29/4966

Abstract: A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in a basal layer, forming a metal layer on the basal layer, exposing the metal layer to a tungsten halide gas to form an oxygen-deficient metal layer, and forming a bulk tungsten layer on the oxygen-deficient metal layer.

公开(公告)号：US20240363627A1

公开(公告)日：2024-10-31

申请号：US18767022

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Chang Chiu ,  Chia-Ching Lee ,  Chien-Hao Chen ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chi On Chui ,  Hsuan-Yu Tung ,  Chung-Chiang Wu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/6681 ,  H01L29/785

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

公开(公告)号：US12033893B2

公开(公告)日：2024-07-09

申请号：US18359016

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hsueh Wen Tsau ,  Chia-Ching Lee ,  Cheng-Lung Hung ,  Ching-Hwanq Su

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76871 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.

公开(公告)号：US20240222108A1

公开(公告)日：2024-07-04

申请号：US18608560

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Chung-Chiang Wu ,  Shih-Hang Chiu ,  Hsuan-Yu Tung ,  Da-Yuan Lee

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/02175 ,  H01L21/76841 ,  H01L21/76871 ,  H01L27/0886 ,  H01L29/66871

Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

公开(公告)号：US20230155002A1

公开(公告)日：2023-05-18

申请号：US17700998

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hang Chiu ,  Wei-Cheng Wang ,  Chung-Chiang Wu ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/0259 ,  H01L21/28088 ,  H01L29/0665 ,  H01L29/4908 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: Embodiments provide a replacement metal gate in a FinFET or nanoFET which utilizes a conductive metal fill. The conductive metal fill has an upper surface which has a fin shape which may be used for a self-aligned contact.