公开(公告)号：US20200020588A1

公开(公告)日：2020-01-16

申请号：US16578357

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Ting Yang ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Meng-Hung Shen ,  Ru-Gun Liu ,  Wei-Cheng Lin

IPC: H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.

公开(公告)号：US10520303B2

公开(公告)日：2019-12-31

申请号：US15811272

申请日：2017-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chui-Jung Chiu ,  Jen-Chieh Lo ,  Ying-Chou Cheng ,  Ru-Gun Liu

IPC: G01B15/04 ,  G01B15/00 ,  H01J37/28

Abstract: A method includes receiving, into a measurement tool, a substrate having a material feature, wherein the material feature is formed on the substrate according to a design feature. The method further includes applying a source signal on the material feature, collecting a response signal from the material feature by using a detector in the measurement tool to obtain measurement data, and with a computer connected to the measurement tool, calculating a simulated response signal from the design feature. The method further includes, with the computer, in response to determining that a difference between the collected response signal and the simulated response signal exceeds a predetermined value, causing the measurement tool to re-measure the material feature.

公开(公告)号：US10418252B2

公开(公告)日：2019-09-17

申请号：US15382035

申请日：2016-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yuan Tseng ,  Wei-Liang Lin ,  Hsin-Chih Chen ,  Shi Ning Ju ,  Ken-Hsien Hsieh ,  Yung-Sung Yen ,  Ru-Gun Liu

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311

Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).

公开(公告)号：US10276499B2

公开(公告)日：2019-04-30

申请号：US15714172

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Peng ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Yung-Sung Yen

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02

Abstract: In some embodiments, the present disclosure relates to an integrated chip having a lower power rail continuously extending over a plurality of gate structures. A first set of connection pins straddle a first edge of the lower power rail, and a second set of connection pins straddle a second edge of the lower power rail, which is opposite the first edge. The first set of connection pins and the second set of connection pins are electrically coupled to the lower power rail. An upper power rail is over the lower power rail and is electrically coupled to the first set of connection pins and the second set of connection pins. The first set of connection pins are arranged at a first pitch and the second set of connection pins arranged with respect to the first set of connection pins at a second pitch less than the first pitch.

公开(公告)号：US10276394B2

公开(公告)日：2019-04-30

申请号：US15704367

申请日：2017-09-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Hsien Hsieh ,  Wen-Li Cheng ,  Dong-Yo Jheng ,  Chih-Ming Lai ,  Ru-Gun Liu

IPC: G06F7/50 ,  H01L21/308 ,  G06F17/50

Abstract: A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.

公开(公告)号：US20190094680A1

公开(公告)日：2019-03-28

申请号：US15813774

申请日：2017-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Ting Huang ,  Chih-Shiang Chou ,  Ru-Gun Liu

IPC: G03F1/36 ,  G06F17/50 ,  H01L21/027 ,  H01L21/66 ,  G03F1/78 ,  G03F1/80 ,  G03F7/16 ,  G03F7/20 ,  G03F7/38 ,  G03F7/26

Abstract: The present disclosure provides an integrated circuit (IC) method in accordance with some embodiments. The method includes building a mask model to simulate a mask image and a compound lithography computational model to simulate a wafer pattern; calibrating the mask model using a measured mask image; calibrating the compound lithography computational model using a measured wafer data and the calibrated mask model; and performing an optical proximity correction (OPC) process to an IC pattern using the calibrated compound computational model, thereby generating a mask pattern for mask fabrication.

公开(公告)号：US10096522B2

公开(公告)日：2018-10-09

申请号：US15148274

申请日：2016-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Ting Yang ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Meng-Hung Shen ,  Ru-Gun Liu ,  Wei-Cheng Lin

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: The present disclosure relates to a method of forming an integrated chip having middle-of-the-line (MOL) structures arranged at an irregular pitch, and an associated method of formation. In some embodiments, the integrated chip has a well region with a plurality of source/drain regions. A plurality of gate structures are arranged over the well region at a regular pitch. A plurality of middle-of-the-line (MOL) structures are laterally interleaved between some of the plurality of gate structures and are arranged over the well region at an irregular pitch having a first pitch that is larger than the regular pitch. Since the MOL structures have an irregular pitch with a first pitch that is larger than the regular pitch, one or more of the plurality of gate structures are spaced apart from a closest gate or MOL structure by a space that reduces parasitic capacitance.

公开(公告)号：US20180285512A1

公开(公告)日：2018-10-04

申请号：US15997513

申请日：2018-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Ting Huang ,  Shuo-Yen Chou ,  Ru-Gun Liu

IPC: G06F17/50 ,  G03F1/78

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G03F1/78 ,  G06F17/5068 ,  G06F2217/12

Abstract: Source beam optimization (SBO) methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an IC design layout and performing an SBO process using the IC design layout to generate a mask shot map and an illumination source map. The SBO process uses an SBO model that collectively simulates a mask making process using the mask shot mask and a wafer making process using the illumination source map. A mask can be fabricated using the mask shot map, and a wafer can be fabricated using the illumination source map (and, in some implementations, using the mask fabricated using the mask shot map). The wafer includes a final wafer pattern that corresponds with a target wafer pattern defined by the IC design layout. SBO methods disclosed herein can significantly reduce (or eliminate) variances between the final wafer pattern and the target wafer pattern.

公开(公告)号：US10083270B2

公开(公告)日：2018-09-25

申请号：US15379084

申请日：2016-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Shuo-Yen Chou ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: Target optimization methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an IC design layout for a target pattern, wherein the target pattern has a corresponding target contour; modifying the target pattern, wherein the modified target pattern has a corresponding modified target contour; and generating an optimized target pattern when the modified target contour achieves functionality of the target pattern as defined by a constraint layer. The method can further include defining a cost function based on the constraint layer, where the cost function correlates a spatial relationship between a contour of the target pattern and the constraint layer.

公开(公告)号：US10049918B2

公开(公告)日：2018-08-14

申请号：US15395310

申请日：2016-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Cheng Hung ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ta-Ching Yu ,  Yung-Sung Yen ,  Ziwei Fang ,  Tsai-Sheng Gau ,  Chin-Hsiang Lin ,  Kuei-Shun Chen

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L21/3115

Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof. In some implementations, the directional patterning method disclosed herein can achieve oblique interconnects and/or slot (rectangular) via interconnects.