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公开(公告)号：US09153343B2
公开(公告)日：2015-10-06
申请号：US14079386
申请日：2013-11-13
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Wen-Ting Chu , Yue-Der Chih
CPC classification number: G11C29/76 , G11C13/0002 , G11C13/0021 , G11C13/0023 , G11C13/0069 , G11C29/027 , G11C2029/4402
Abstract: A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells.
Abstract translation: 本文公开了一种设备，其包括存储区域和基于电阻读取存取存储器（基于RRAM或基于ReRAM的）非易失性存储阵列。 存储区域包括第一存储阵列和第二存储阵列。 第一存储阵列包括多个第一存储单元。 第二存储阵列包括多个第二存储单元。 第二存储单元被配置为代替第一存储单元。 基于RRAM的非易失性存储阵列被配置为记录第一存储单元和第二存储单元之间的至少一个对应关系。
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公开(公告)号：US20150269997A1
公开(公告)日：2015-09-24
申请号：US14219350
申请日：2014-03-19
Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
Inventor： Kai-Chun Lin , Hung-Chang Yu , Ku-Feng Lin , Yue-Der Chih
IPC: G11C13/00
CPC classification number: G11C11/1655 , G11C11/1659 , G11C11/1675 , G11C11/1697 , G11C13/0026 , G11C13/0069 , G11C2013/0083 , G11C2213/79 , G11C2213/82
Abstract: A circuit that includes a current source module, a current sink module and a memory bank is disclosed. Each of the current source module, the current sink module and the memory bank is connected to the first bit/source line and the second bit/source line. The memory bank is bounded by the current source module and the current sink module. When the current source module and the current sink module receive a triggering pulse from the first bit/source line and a select signal with a first state, the current source module is activated to generate an operating current to the first bit/source line that transmits through a conducted memory cell of the memory bank and the current sink module is activated to drain the operating current from the second bit/source line.
Abstract translation: 公开了一种包括电流源模块，电流吸收模块和存储体的电路。 电流源模块，电流模块和存储器组中的每一个都连接到第一位/源极线和第二位/源极线。 存储体由当前的源模块和当前的模块组成。 当电流源模块和电流接收模块从第一位/源线接收到触发脉冲和具有第一状态的选择信号时，电流源模块被激活以产生到第一位/源线的工作电流， 通过存储体的传导存储单元并且激活电流吸收模块以从第二位/源极线中漏去工作电流。
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Patent Agency Ranking
公开(公告)号：US09110829B2
公开(公告)日：2015-08-18
申请号：US13917772
申请日：2013-06-14
Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
Inventor： Yue-Der Chih , Hung-Chang Yu , Kai-Chun Lin , Chin-Yi Huang , Laun C. Tran
CPC classification number: G06F11/1056 , G06F11/10 , G06F11/1004 , G06F11/1048 , G06F11/1052 , G06F11/1402 , G06F11/141 , G11C11/1675 , G11C11/1677 , G11C2013/0076 , H03M13/11 , H03M13/611
Abstract: Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location.
Abstract translation: 本公开的一些方面涉及一种方法。 该方法尝试将期望的多位字写入存储器中的存储器位置。 在尝试写入多位字之后，从存储器位置读取实际的多位字。 然后将实际的多位字与期望的多位字进行比较，以识别存储在存储器位置中的错误位数和数量的正确位。 错误位的数量被重写到存储器位置，而不尝试将正确的位重写到存储器位置。
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公开(公告)号：US20150206583A1
公开(公告)日：2015-07-23
申请号：US14161193
申请日：2014-01-22
Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
Inventor： Chung-Cheng Chou , Yue-Der Chih
CPC classification number: G11C13/0064 , G11C11/56 , G11C13/0007 , G11C13/0069 , G11C2013/0066 , G11C2013/0078 , G11C2213/79 , H03K17/56
Abstract: A circuit that includes a current source and a current comparator is disclosed. The current source is connected to a resistive memory cell to generate a driving current thereto. The current comparator has a sensing node connected to the current source and the resistive memory cell to sense an injection current injected to the current comparator through the sensing node, wherein when a resistive state of the resistive memory cell switches such that the current comparator determines that an amount of the injection current increases to exceed or decreases to reach threshold value, the current comparator turns off the current source.
Abstract translation: 公开了一种包括电流源和电流比较器的电路。 电流源连接到电阻存储器单元以产生驱动电流。 电流比较器具有连接到电流源和电阻存储器单元的感测节点，以感测通过感测节点注入到电流比较器的注入电流，其中当电阻性存储器单元的电阻状态切换使得电流比较器确定 注入电流的量增加到超过或者减小到达阈值时，电流比较器关闭电流源。
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公开(公告)号：US09047956B2
公开(公告)日：2015-06-02
申请号：US14014471
申请日：2013-08-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tien-Chun Yang , Chia-Fu Lee , Yue-Der Chih
CPC classification number: G11C16/06 , G11C16/30 , G11C2216/22
Abstract: A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.
Abstract translation: 设备包括地址存储设备。 第一电路包括第一闪存，其被配置为顺序地接收第一和第二地址并将第一地址存储在地址存储设备中。 第一电路具有第一组控制输入，用于使第一电路从与第一和第二地址中所选择的一个对应的第一闪存的单元上的读取，编程和擦除组合执行第一操作。 第二电路包括被配置为接收第二地址的第二闪存。 第二电路具有第二组控制输入，用于在执行第一操作时使第二电路从对应于第二地址的第二闪速存储器的单元读取数据。
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公开(公告)号：US20140157088A1
公开(公告)日：2014-06-05
申请号：US13917772
申请日：2013-06-14
Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
Inventor： Yue-Der Chih , Hung-Chang Yu , Kai-Chun Lin , Chin-Yi Huang , Laun C. Tran
CPC classification number: G06F11/1056 , G06F11/10 , G06F11/1004 , G06F11/1048 , G06F11/1052 , G06F11/1402 , G06F11/141 , G11C11/1675 , G11C11/1677 , G11C2013/0076 , H03M13/11 , H03M13/611
Abstract: Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location.
Abstract translation: 本公开的一些方面涉及一种方法。 该方法尝试将期望的多位字写入存储器中的存储器位置。 在尝试写入多位字之后，从存储器位置读取实际的多位字。 然后将实际的多位字与期望的多位字进行比较，以识别存储在存储器位置中的错误位数和数量的正确位。 错误位的数量被重写到存储器位置，而不尝试将正确的位重写到存储器位置。
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公开(公告)号：US08565023B2
公开(公告)日：2013-10-22
申请号：US13670607
申请日：2012-11-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tien-Chun Yang , Chia-Fu Lee , Yue-Der Chih
IPC: G11C16/04
CPC classification number: G11C16/06 , G11C16/30 , G11C2216/22
Abstract: A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.
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