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    Semiconductor memory device including a data transfer circuit for transferring data between a DRAM and an SRAM
    22.
    发明授权
    Semiconductor memory device including a data transfer circuit for transferring data between a DRAM and an SRAM 失效
    半导体存储器件包括用于在DRAM和SRAM之间传送数据的数据传输电路

    公开(公告)号：US5603009A

    公开(公告)日：1997-02-11

    申请号：US356046

    申请日：1994-12-14

    申请人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

    发明人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

    IPC分类号： G06F12/08 ,  G11C7/10 ,  G11C11/00 ,  G06F13/00 ,  G11C11/34

    CPC分类号： G11C7/1006 ,  G06F12/0893 ,  G11C11/005 ,  G11C7/103 ,  G11C7/1045 ,  G11C2207/2254

    摘要： A semiconductor memory device containing a cache includes a static random access memory (SRAM) as a cache memory, and a dynamic random access memory (DRAM) as a main memory. Collective transfer of data blocks is possible between the DRAM and the SRAM through a bi-directional data transfer gate circuit and through an internal data line. A DRAM row decoder and a DRAM column decoder are provided in the DRAM. A SRAM row decoder and an SRAM column decoder are provided in the SRAM. Addresses of the SRAM and DRAM can be independently applied. The data transfer gate includes a latch circuit for latching data from the SRAM, which serves as a high speed memory, an amplifier circuit and a gate circuit for amplifying data from the DRAM, which serves as a large capacity memory, and for transmitting the amplified data to the SRAM, and a gate circuit, responsive to a DRAM write enable signal for transmitting write data to corresponding memory cells of the DRAM. After the data of the SRAM has been latched by a latch circuit, write data is transmitted from the gate circuit to the DRAM, and the write data is transmitted to the SRAM through the amplifier circuit and the gate circuit.

    摘要翻译： 包含高速缓存的半导体存储器件包括作为高速缓冲存储器的静态随机存取存储器（SRAM）和作为主存储器的动态随机存取存储器（DRAM）。 通过双向数据传输门电路和内部数据线，可以在DRAM和SRAM之间进行数据块的集中传输。 在DRAM中提供DRAM行解码器和DRAM列解码器。 在SRAM中提供SRAM行解码器和SRAM列解码器。 SRAM和DRAM的地址可以独立应用。 数据传输门包括一个锁存电路，用于锁存来自用作高速存储器的SRAM的数据，放大器电路和用于放大来自DRAM的数据的门电路，其用作大容量存储器，并用于发送放大 数据到SRAM，以及门电路，响应于用于将写入数据发送到DRAM的相应存储器单元的DRAM写使能信号。 在SRAM的数据被锁存电路锁存之后，写入数据从门电路传输到DRAM，写数据通过放大电路和门电路传输到SRAM。

    Circuit having charge compensation and an operation method of the same
    23.
    发明授权
    Circuit having charge compensation and an operation method of the same 失效
    具有电荷补偿的电路及其操作方法

    公开(公告)号：US5151614A

    公开(公告)日：1992-09-29

    申请号：US725037

    申请日：1991-07-03

    申请人： Akira Yamazaki ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka

    发明人： Akira Yamazaki ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H03K3/356 ,  H03K17/22

    CPC分类号： H03K3/356008 ,  H03K17/223 ,  H01L2924/0002

    摘要： A residual charge removing circuit connected to a node in a power-on reset pulse generating circuit for removing positive charges which remain in this node when a power supply is turned off is disclosed. This residual charge removing circuit is formed of two N-channel MOS transistors connected in series between the node and the ground, and one capacitor. Out of the two N-channel MOS transistors, the transistor near the node has a grounded gate. The capacitor is connected between a gate of the transistor, out of the two N-channel MOS transistors, which is distant from the node, and a power supply. The gate of the transistor distant from the node is connected to a connection point between the two N-channel MOS transistors. Therefore, when a supply potential lowers below a threshold voltage Vth of the MOS transistors due to the power-off, the transistor distant from the node is turned off, so that a potential of the connection point becomes -Vth owing to a discharge of negative charges from the capacitor. This turns on the transistor near the node, so that the residual charges in the node are offset by the negative charges in the connection point.

    摘要翻译： 公开了一种连接到上电复位脉冲发生电路中的节点的剩余电荷去除电路，用于去除当电源关闭时保留在该节点中的正电荷。 该剩余电荷去除电路由串联在节点和地之间的两个N沟道MOS晶体管和一个电容器组成。 在两个N沟道MOS晶体管中，节点附近的晶体管具有接地栅极。 电容器连接在离节点的两个N沟道MOS晶体管中的晶体管的栅极和电源之间。 远离节点的晶体管的栅极连接到两个N沟道MOS晶体管之间的连接点。 因此，当电源电压由于断电而降低到MOS晶体管的阈值电压Vth以下时，远离节点的晶体管截止，使得由于放电为负的连接点的电位变为-Vth 从电容器充电。 这使得节点附近的晶体管导通，使得节点中的剩余电荷被连接点中的负电荷抵消。

    Synchronous semiconductor memory including register for storing data input and output mode information
    25.
    发明授权
    Synchronous semiconductor memory including register for storing data input and output mode information 失效
    同步半导体存储器包括用于存储数据输入和输出模式信息的寄存器

    公开(公告)号：US06434661B1

    公开(公告)日：2002-08-13

    申请号：US09640518

    申请日：2000-08-17

    申请人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

    发明人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

    IPC分类号： G06F1300

    CPC分类号： G11C7/1006 ,  G06F12/0893 ,  G11C7/103 ,  G11C7/1045 ,  G11C11/005 ,  G11C2207/2254

    摘要： A semiconductor memory device is provided with a static random access memory (SRAM) serving as a cache memory and a dynamic random access memory (DRAM) serving as a main memory. A bi-directional data transfer circuit is arranged for transfer of data blocks between the SRAM and the DRAM. A command register is provided for holding command data to set operation modes such as a data output mode of the memory device. The data output mode may include a transparent mode, a latched mode and a registered mode selected depending on a data combination at data input terminals of the memory device. An output circuit for providing a selected data output mode includes an output latch circuit for latching data on read data buses in response to clock signals, and an output buffer for outputting data from the output latches to a data output terminal. The latch circuit provides data at a first clock cycle of a clock signal when the command data has a first value and provides data at a second clock cycle of the clock signal, which is later than the first clock cycle, when the command data has a second value.

    摘要翻译： 半导体存储器件具有用作高速缓冲存储器的静态随机存取存储器（SRAM）和用作主存储器的动态随机存取存储器（DRAM）。 双向数据传输电路被布置用于在SRAM和DRAM之间传送数据块。 提供了一个命令寄存器来保存命令数据以设置诸如存储器件的数据输出模式的操作模式。 数据输出模式可以包括根据存储器件的数据输入端子处的数据组合选择的透明模式，锁存模式和注册模式。 用于提供选择的数据输出模式的输出电路包括用于响应于时钟信号在读取数据总线上锁存数据的输出锁存电路，以及用于将数据从输出锁存器输出到数据输出端的输出缓冲器。 当命令数据具有第一值时，锁存电路以时钟信号的第一时钟周期提供数据，并且当命令数据具有第一时钟周期时，提供比第一时钟周期晚的时钟信号的第二时钟周期的数据 第二个值。

    Semiconductor memory device
    26.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06356484B2

    公开(公告)日：2002-03-12

    申请号：US09480006

    申请日：2000-01-10

    申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Ishizuka ,  Tsukasa Saika

    发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Ishizuka ,  Tsukasa Saika

    IPC分类号： G11C1100

    CPC分类号： G11C8/00 ,  G06F12/0893 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02D10/13

    摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

    摘要翻译： 半导体存储器件包括DRAM，SRAM和设置在SRAM和DRAM之间的双向传输门电路。 SRAM阵列包括多组字线。 在SRAM阵列的每行中提供每组，并且每组中的每个字线连接到相关行的不同组的存储单元。 SRAM的地址信号和DRAM的地址信号分别应用于地址缓冲器。 半导体存储器件还包括用于实现突发模式和睡眠模式的附加功能控制电路。 从DRAM到SRAM的数据传输路径以及从SRAM到DRAM的数据传输路径分别设置在双向传输门电路中。 数据写入路径和数据读取路径分别设置在DRAM阵列中。 通过上述结构，在睡眠模式中停止缓冲电路的动作，降低功耗。 由于数据写入路径和数据读取路径分别设置在DRAM阵列中，所以可以以非多路复用的方式应用DRAM阵列的地址，从而数据可以从DRAM阵列以高速传输到SRAM阵列，使得能够高 高速运行即使在缓存未命中。

    Semiconductor memory device
    27.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5652723A

    公开(公告)日：1997-07-29

    申请号：US869917

    申请日：1992-04-15

    申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

    发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

    IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

    CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

    摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

    摘要翻译： 半导体存储器件包括DRAM，SRAM和设置在SRAM和DRAM之间的双向传输门电路。 SRAM阵列包括多组字线。 在SRAM阵列的每行中提供每组，并且每组中的每个字线连接到相关行的不同组的存储单元。 SRAM的地址信号和DRAM的地址信号分别应用于地址缓冲器。 半导体存储器件还包括用于实现突发模式和睡眠模式的附加功能控制电路。 从DRAM到SRAM的数据传输路径以及从SRAM到DRAM的数据传输路径分别设置在双向传输门电路中。 数据写入路径和数据读取路径分别设置在DRAM阵列中。 通过上述结构，在睡眠模式中停止缓冲电路的动作，降低功耗。 由于数据写入路径和数据读取路径分别设置在DRAM阵列中，所以可以以非多路复用的方式应用DRAM阵列的地址，从而数据可以从DRAM阵列以高速传输到SRAM阵列，使得能够高 高速运行即使在缓存未命中。

    Dynamic random access memory device capable of performing test mode operation and method of operating such memory device
    29.
    发明授权
    Dynamic random access memory device capable of performing test mode operation and method of operating such memory device 失效
    能够执行测试模式操作的动态随机存取存储器件以及操作该存储器件的方法

    公开(公告)号：US5270977A

    公开(公告)日：1993-12-14

    申请号：US751934

    申请日：1991-09-03

    申请人： Hisashi Iwamoto ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki

    发明人： Hisashi Iwamoto ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki

    IPC分类号： G01R31/28 ,  G11C7/00 ,  G11C11/401 ,  G11C11/406 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： G11C11/4072 ,  G11C11/46 ,  G11C29/46

    摘要： Disclosed is a DRAM including a test mode operation capable of testing whether a plurality of memory cells are defective or not in a short time. The DRAM includes a power-on detection signal generator, a power-on reset signal generator, and a test mode instruction signal generator. The power-on detection signal generator detects application of a power supply voltage and generates a power-on detection signal. The power-on reset signal generator is reset by a power-on reset signal, counts at least once an external RAS signal applied after reset and generates a power-on reset signal. The test mode instruction signal generator detects logic states of an internal RAS signal, an internal CAS signal and an internal W signal applied after the power-on reset and generates a test mode instructing signal.

    摘要翻译： 公开了一种包括能够在短时间内测试多个存储单元是否有故障的测试模式操作的DRAM。 DRAM包括上电检测信号发生器，上电复位信号发生器和测试模式指令信号发生器。 上电检测信号发生器检测电源电压的应用并产生上电检测信号。 上电复位信号发生器由上电复位信号复位，至少在复位后施加一次外部和上升沿和R信号并产生上电复位信号。 测试模式指令信号发生器检测内部RAS信号，内部CAS信号和上电复位后施加的内部W信号的逻辑状态，并产生测试模式指令信号。