公开(公告)号：US06323794B1

公开(公告)日：2001-11-27

申请号：US09437405

申请日：1999-11-10

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

IPC分类号： H03M300

CPC分类号： H03M7/3022 ,  H03M3/414 ,  H03M3/458 ,  H03M3/50

摘要： Modulators (M1 to Mk (k≧2)) are connected in a multi-stage such that each of quantization errors (e1, e2, . . . ) of the modulators (M1 to Mk−1) is fed to the input of the next stage modulator. Each output signal of the modulators (M2 to Mk) is fed back to the input of the immediately preceding modulator. The modulators (M1 to Mk) are all first-order modulators. Only the final stage modulator (Mk) has a multi-bit quantizer (6), and all the preceding modulators (M1 to Mk−1) have an 1-bit quantizer (3). Accordingly, a noise-shaping equal to that of a multi-bit higher-order modulator is realized on a small-scale circuit while retaining stability.

摘要翻译： 调制器（M1至Mk（k> = 2））以多级连接，使得调制器（M1至Mk-1）的每个量化误差（e1，e2，...）被馈送到 下一级调制器。 调制器（M2至Mk）的每个输出信号被反馈到紧接在前的调制器的输入端。 调制器（M1至Mk）都是一阶调制器。 只有最后级调制器（Mk）具有多位量化器（6），并且所有先前的调制器（M1至Mk-1）都具有1位量化器（3）。 因此，在保持稳定性的同时，在小规模电路上实现等于多位高阶调制器的噪声整形。

公开(公告)号：US06300890B1

公开(公告)日：2001-10-09

申请号：US09716241

申请日：2000-11-21

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

IPC分类号： H03M300

CPC分类号： H03M3/46

摘要： A delta-sigma modulator comprises a 1-bit quantizer located for quantizing an analog signal applied thereto, and for outputting a first quantized digital signal, a 1-bit DA converter converting the first quantized digital signal into a quantized analog signal, a subtracting circuit for subtracting the quantized analog signal output from the 1-bit DA converter from the analog signal input to the 1-bit quantizer, and an input integrating circuit series including a series of one or more stages each of which includes a subtracter and an integrator for integrating an output of the subtracter, one subtracter at a first stage subtracting the quantized analog signal delayed by a delay element from an input analog signal input to the delta-sigma modulator, and one integrator at a final stage outputting its output to the 1-bit quantizer. A multiple-bit quantizer quantizes an analog output of the subtracting circuit and outputs a second quantized digital signal. A differentiator then calculates an Nth-order derivative of the second quantized digital signal from the multiple-bit quantizer, N being equal to a number of the one or more stages included in the input integrating circuit series, and an adder adds an output of the differentiator to the first quantized digital signal from the 1-bit quantizer.

摘要翻译： Δ-Σ调制器包括1位量化器，用于量化施加到其上的模拟信号，并用于输出第一量化数字信号，将第一量化数字信号转换为量化模拟信号的1位DA转换器，减法电路 用于从输入到1位量化器的模拟信号中减去从1位DA转换器输出的量化模拟信号，以及包括一系列一级或多级的输入积分电路系列，每级包括减法器和积分器 对减法器的输出进行积分，一个减法器在第一级从输入到Δ-Σ调制器的输入模拟信号中减去由延迟元件延迟的量化模拟信号，以及一个积分器，将其输出输出到1- 位量化器。 多位量化器量化减法电路的模拟输出并输出第二量化数字信号。 然后，微分器计算来自多位量化器的第二量化数字信号的N次导数，N等于包括在输入积分电路序列中的一个或多个级的数，并且加法器将 与1位量化器的第一个量化数字信号进行微分。

公开(公告)号：US5995031A

公开(公告)日：1999-11-30

申请号：US968207

申请日：1997-11-12

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

IPC分类号： H03M1/10 ,  H03M1/06 ,  H03M1/74 ,  H03M1/66

CPC分类号： H03M1/0663 ,  H03M1/747 ,  H03M3/464 ,  H03M3/502

摘要： A multi-bit D/A converter which improves the linearity of an analog output relative to a digital input is provided. A switch control circuit (1) turns on D some of a plurality of switches (S1 to SM) which are arranged in ascending order starting with a switch determined by a start position determination circuit (3) and turns off the remaining switches, the number of switches turned on being dependent on a digital signal (DIG). The start position determination circuit (3) sequentially changes the switches (S1, S3, S5, . . . ) serving as a selection start position to determine the selection start position for each input of the digital signal (DIG) provided in synchronism with a clock signal (CLK).

摘要翻译： 提供了一种提高模拟输出相对于数字输入的线性度的多位D / A转换器。 开关控制电路（1）接通D开始的开关位置确定电路（3）确定的开关的升序排列的多个开关（S1至SM）中的一些，并且关闭其余的开关 开关依赖于数字信号（DIG）。 开始位置确定电路（3）顺序地改变用作选择开始位置的开关（S1，S3，S5 ...），以确定与设置的与数字信号（DIG）同步的数字信号（DIG）的每个输入的选择开始位置 时钟信号（CLK）。

公开(公告)号：US5629700A

公开(公告)日：1997-05-13

申请号：US552016

申请日：1995-11-02

申请人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

发明人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

IPC分类号： H03M1/14 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/16 ,  H03M1/44 ,  H03M1/34

CPC分类号： H03M1/002 ,  H03M1/0682 ,  H03M1/069 ,  H03M1/1215 ,  H03M1/167

摘要： An A/D converter block A/D1 converts an analog input signal Vin to a digital signal and outputs its D/A output. First SH/SUBT7, 8 sample the signal Vin and a voltage VRM at the same timing with said A/D conversion and output the results of subtraction of the respective sampling values and the D/A output during holding, respectively. The both results of subtraction are several tens mV and there is no need of taking account of the linearity of a differential amplifier DIFF11. During the sampling, a circuit SHR1 outputs the differential voltages between each reference tap voltage taken out from specific 2 points of the ladder-type resistor in the A/D converter block A/D1 and the voltage VRM while a differential amplifier DIFF12 applies the reference voltages to the next A/D converter block A/D2. Such operations are performed in each stage. Thus, it becomes possible to make any S/H circuit and amplifier of excellent linearity in the first stage unnecessary to reduce the electric power consumption.

摘要翻译： A / D转换器模块A / D1将模拟输入信号Vin转换为数字信号并输出​​其D / A输出。 第一SH / SUBT7,8以与所述A / D转换相同的定时采样信号Vin和电压VRM，并分别输出相应采样值和保持期间的D / A输出的结果。 减法的结果都是几十mV，不需要考虑差分放大器DIFF11的线性度。 在采样期间，电路SHR1输出从A / D转换器模块A / D1中的梯形电阻器的特定2点取出的每个参考分接电压与电压VRM之间的差分电压，而差分放大器DIFF12施加参考 电压到下一个A / D转换器模块A / D2。 这样的操作在每个阶段进行。 因此，可以使得在第一级中具有优异线性度的任何S / H电路和放大器不必减少电力消耗。

公开(公告)号：US08237282B2

公开(公告)日：2012-08-07

申请号：US13030861

申请日：2011-02-18

申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L23/522

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

公开(公告)号：US07952506B2

公开(公告)日：2011-05-31

申请号：US12911286

申请日：2010-10-25

申请人： Toshio Kumamoto ,  Takashi Okuda ,  Tatsuo Sengoku ,  Akira Kitaguchi

发明人： Toshio Kumamoto ,  Takashi Okuda ,  Tatsuo Sengoku ,  Akira Kitaguchi

IPC分类号： H03M3/00

CPC分类号： H03M3/328 ,  H03M3/33 ,  H03M3/43 ,  H03M3/452

摘要： There is provided a technique for reducing the adverse effect of idle tones in the channels in a ΔΣ-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ΔΣ-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.

摘要翻译： 提供了一种用于减少包括用于将模拟输入信号转换为数字信号的多个通道的＆Dgr＆amp; S型A / D转换器中的通道中的空闲音调的不利影响的技术。 ＆amp; S＆amp; S型A / D转换器包括用于将左模拟输入信号转换为数字信号的L通道和用于将右模拟输入信号转换为数字信号的R通道。 L沟道和R沟道中的每一个包括用于产生用于移动空闲频率的频率的DC附加电压的DC抖动电路。 在L沟道和R沟道中，由DC抖动电路产生的直流相加电压彼此不同。

公开(公告)号：US20110068383A1

公开(公告)日：2011-03-24

申请号：US12958923

申请日：2010-12-02

申请人： Takashi Okuda ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Toshio Kumamoto

IPC分类号： H01L27/06

CPC分类号： H01L23/585 ,  H01L27/0248 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.

摘要翻译： 本发明的目的是确保将模拟块中的预定半导体元件或预定半导体元件组与数字块产生的噪声保护起来。 根据本发明的半导体器件包括半导体衬底，作为形成数字电路的区域的数字块和形成模拟电路的区域的模拟块，通过将模拟电路的上表面 半导体基板和设置在半导体基板上的基板电位固定区域，以在平面图中包围模拟块中的预定半导体元件组，以及连接到基板电位固定区域并从外部接收预定电位的焊盘 部分。

公开(公告)号：US20100109775A1

公开(公告)日：2010-05-06

申请号：US12570650

申请日：2009-09-30

申请人： Masaomi KAMAKURA ,  Toshio Kumamoto ,  Takashi Okuda

发明人： Masaomi KAMAKURA ,  Toshio Kumamoto ,  Takashi Okuda

IPC分类号： H03F3/45 ,  H01C1/012 ,  H03F3/04

CPC分类号： H03F3/45475 ,  H01L27/0802 ,  H01L28/20 ,  H03F2203/45528 ,  H03F2203/45594 ,  H03F2203/45602

摘要： To eliminate the substrate voltage dependences of the respective resistance values of resistor elements, in the resistor elements coupled in series to each other over respective substrate regions, the ends of the resistor elements are coupled to the corresponding substrate regions by respective bias wires such that respective average potentials between the substrate regions of the resistor elements and the corresponding resistor elements have opposite polarities, and equal magnitudes.

摘要翻译： 为了消除电阻元件的相应电阻值的衬底电压依赖性，在电阻元件中在各个衬底区域上彼此串联耦合的电阻器元件中，电阻器元件的端部通过相应的偏置线耦合到相应的衬底区域， 电阻元件的基板区域和对应的电阻元件之间的平均电位具有相反的极性和相等的幅度。

公开(公告)号：US20090250788A1

公开(公告)日：2009-10-08

申请号：US12485528

申请日：2009-06-16

申请人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction, a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 形成在主表面上并沿预定方向延伸的电容形成区域中的多个第一互连，多个第二互连，每个第二互连相邻于位于电容形成区域边缘的第一互连件，沿预定方向延伸; 并具有固定的潜力; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

公开(公告)号：US07446390B2

公开(公告)日：2008-11-04

申请号：US11845348

申请日：2007-08-27

申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。