公开(公告)号：US20050094426A1

公开(公告)日：2005-05-05

申请号：US10995124

申请日：2004-11-24

申请人： Yutaka Terada ,  Takefumi Yoshikawa

发明人： Yutaka Terada ,  Takefumi Yoshikawa

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C5/06

CPC分类号： G11C7/1093 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/22

摘要： An input circuit includes: a comparator; first and second delay circuits; a selector; an input buffer; and a holding circuit. The comparator compares the leading and/or trailing edges of a data signal, supplied from the input buffer, to an edge of a clock signal on which the data signal is intended to be latched. Based on the results of the comparison, the first and second delay circuits delay the clock signal for respectively predetermined amounts of time. If the data signal is logically high, then the selector selects a delayed clock signal supplied from the first delay circuit. Alternatively, if the data signal is logically low, then the selector selects another delayed clock signal supplied from the second delay circuit. Then, the delayed clock signal, selected by the selector, is latched in the holding circuit. The input circuit with such a configuration prevents skewing from being caused by a difference in length between the transition interval of the data signal from H into L level and that of the data signal from L into H level. As a result, data can be transferred at a much higher speed even if the clock frequency is very high.

摘要翻译： 输入电路包括：比较器; 第一和第二延迟电路; 选择器 一个输入缓冲区; 和保持电路。 比较器将从输入缓冲器提供的数据信号的前沿和/或后沿比较到要锁存数据信号的时钟信号的边沿。 基于比较结果，第一和第二延迟电路将时钟信号分别延迟预定的时间量。 如果数据信号逻辑高，则选择器选择从第一延迟电路提供的延迟时钟信号。 或者，如果数据信号在逻辑上低，则选择器选择从第二延迟电路提供的另一延迟时钟信号。 然后，由选择器选择的延迟时钟信号被锁存在保持电路中。 具有这种配置的输入电路防止由数据信号从H变为L电平的过渡间隔和从L变为H电平的数据信号之间的长度差引起的偏移。 因此，即使时钟频率非常高，也可以以更高的速度传输数据。

公开(公告)号：US06393520B2

公开(公告)日：2002-05-21

申请号：US09061331

申请日：1998-04-17

申请人： Takefumi Yoshikawa ,  Hironori Akamatsu ,  Satoshi Takahashi

发明人： Takefumi Yoshikawa ,  Hironori Akamatsu ,  Satoshi Takahashi

IPC分类号： G06F1200

CPC分类号： G09G5/363 ,  G06F12/08 ,  G09G5/39 ,  G09G5/393 ,  G09G2340/125 ,  G09G2352/00 ,  G09G2360/12 ,  G09G2360/121 ,  H04N19/423 ,  H04N19/61

摘要： A processing unit for carrying out specified data processing operations while performing read/write operations on data in an internal memory is coupled to a memory control unit for performing read/write operations on data in an external memory. Data exchange is carried out between the internal and external memories through the memory control unit. Data requiring a longer processing time or data frequently accessed is mapped into the internal memory in accordance with the data exchange, thereby improving overall memory system performance.

摘要翻译： 用于在对内部存储器中的数据执行读/写操作的同时执行指定数据处理操作的处理单元被耦合到用于对外部存储器中的数据执行读/写操作的存储器控​​制单元。 通过存储器控制单元在内部和外部存储器之间进行数据交换。 根据数据交换，需要更长处理时间或经常访问的数据的数据被映射到内部存储器中，从而提高整体存储器系统的性能。

公开(公告)号：US08301093B2

公开(公告)日：2012-10-30

申请号：US12601433

申请日：2008-02-26

申请人： Takefumi Yoshikawa

发明人： Takefumi Yoshikawa

IPC分类号： H04B3/36 ,  H04B5/00 ,  H03D7/16 ,  H04B1/28

CPC分类号： H03K19/018507 ,  H03K3/356017 ,  H03K5/06 ,  H03K5/133 ,  H03K2005/00058 ,  H03K2005/00241 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/08 ,  H04L25/493

摘要： A receiver circuit which can suppress a voltage amplitude appearing on a transmission line. The receiver circuit, coupled to a first and a second transmission lines which transmit information by using currents, includes a first and a second current sources, a first and a second conversion sections which convert currents which flow respectively therein to voltages, a first transistor whose source is coupled to the first current source and to the first transmission line, and whose drain is coupled to the first conversion section, and a second transistor whose source is coupled to the second current source and to the second transmission line, and whose drain is coupled to the second conversion section. The gate and the drain of the first transistor are respectively coupled to the drain and the gate of the second transistor.

摘要翻译： 一种可以抑制出现在传输线上的电压振幅的接收机电路。 耦合到通过使用电流传输信息的第一和第二传输线的接收机电路包括第一和第二电流源，第一和第二转换部分，其将分别流入其中的电流转换成电压;第一晶体管， 源极耦合到第一电流源和第一传输线，并且其漏极耦合到第一转换部分，以及第二晶体管，其源极耦合到第二电流源和第二传输线，并且其漏极是 耦合到第二转换部分。 第一晶体管的栅极和漏极分别耦合到第二晶体管的漏极和栅极。

公开(公告)号：US20060129318A1

公开(公告)日：2006-06-15

申请号：US10540022

申请日：2003-12-26

申请人： Yuji Mizuguchi ,  Nobuhiko Yasui ,  Noboru Katta ,  Takahisa Sakai ,  Yutaka Takahira ,  Hirotsugu Kawada ,  Toshitomo Umei ,  Takashi Akita ,  Takefumi Yoshikawa ,  Shiro Dosho

发明人： Yuji Mizuguchi ,  Nobuhiko Yasui ,  Noboru Katta ,  Takahisa Sakai ,  Yutaka Takahira ,  Hirotsugu Kawada ,  Toshitomo Umei ,  Takashi Akita ,  Takefumi Yoshikawa ,  Shiro Dosho

IPC分类号： G06F19/00

CPC分类号： H04L7/0334 ,  H04L7/005 ,  H04L7/027 ,  H04L7/033

摘要： To a data reception device, a signal having a frequency of 12.5 MHz and including data is transmitted. The data reception device generates a clock B having a frequency of 400 MHz of (1) in FIG. 8, and performs sampling for the above-described 12.5 MHz signal based on the clock B ((2) in FIG. 8). Then, the data reception device detects zero cross points of the sampled data, and generates a 25 MHz frequency clock signal indicating the zero cross points ((3) in FIG. 8). Next, the data reception device generates, by delaying the generated clock signal by the time amount corresponding to eight clocks ((4) in FIG. 8), a 25 MHz signal indicating symbol points. Thus, symbol points can be detected.

摘要翻译： 向数据接收装置发送频率为12.5MHz并包括数据的信号。 数据接收装置在图1中生成具有400MHz的频率的时钟B（1）。 基于时钟B（图8的（2））对上述12.5MHz信号进行采样。 然后，数据接收装置检测取样数据的零交叉点，生成表示零交叉点（图8的（3））的25MHz频率时钟信号。 接下来，数据接收装置通过将生成的时钟信号延迟与8个时钟（图8的（4））对应的时间量来生成表示符号点的25MHz信号。 因此，可以检测符号点。

公开(公告)号：US20050135505A1

公开(公告)日：2005-06-23

申请号：US11000224

申请日：2004-12-01

申请人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa ,  Yukio Arima

发明人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa ,  Yukio Arima

IPC分类号： H03C3/00 ,  H03K7/06 ,  H03L7/093 ,  H04B15/02 ,  H04B3/46

CPC分类号： H04B15/02 ,  H03K7/06 ,  H04B2215/067

摘要： The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.

摘要翻译： 频率调制电路包括：相移部，用于接收由多个时钟信号组成的多相时钟信号，所述多个时钟信号具有预定的相位差，并移位多相时钟信号的相位; 时钟选择部分，用于选择构成从相移部分输出的多相时钟信号的时钟信号; 以及调制控制部分，用于控制相移部分和时钟选择部分，使得从时钟选择部分输出具有与输入到相移部分的多相时钟信号的频率不同的频率的时钟信号。

公开(公告)号：US06735710B1

公开(公告)日：2004-05-11

申请号：US09655717

申请日：2000-09-05

申请人： Takefumi Yoshikawa

发明人： Takefumi Yoshikawa

IPC分类号： G06F104

CPC分类号： H04L7/0337 ,  H03L7/0995 ,  H04L7/042

摘要： Incoming serial data is quantized by 3-times oversampling to obtain a first datastream. By the EXOR of adjacent bits in the datastream, a second datastream which specifies transient points in the first datastream is produced from the first datastream. Reference is made to the third bit from each transient point in the second datastream and to bits positioned on each side of the third bit. If there exists no transient point in any one of these two bits, then the third bit is a boundary. On the other hand, if there exists a transient point in either of the two bits, the bit where the transient point exists is a boundary. In this way, a third datastream is produced. Then, the time-series EXOR of the third datastream and a clock bitstream is performed to produce a final clock bitstream.

摘要翻译： 通过3次过采样对进入的串行数据进行量化以获得第一数据流。 通过数据流中相邻位的EXOR，从第一数据流产生指定第一数据流中的瞬时点的第二数据流。 参考第二个数据流中每个瞬态点的第三位和位于第三位的每一侧的位。 如果在这两个位中的任何一个中不存在瞬态点，则第三位是边界。 另一方面，如果在两个位中的任一位存在瞬态点，则存在瞬态点的位是边界。 以这种方式，产生第三数据流。 然后，执行第三数据流的时间序列EXOR和时钟比特流以产生最终的时钟比特流。

公开(公告)号：US06690217B2

公开(公告)日：2004-02-10

申请号：US10139327

申请日：2002-05-07

申请人： Takefumi Yoshikawa

发明人： Takefumi Yoshikawa

IPC分类号： H03K3017

CPC分类号： H03K5/1565 ,  H04L25/08

摘要： The data width corrector of the invention adjusts the data width appropriately even for data in which cross points have already deviated at the time of input. A data adjusting buffer changes a differential signal received from outside to single-phase receive data and outputs the receive data. A charge pump compares the average time of the HIGH period between the receive data and latch data latched with a latch clock having the same frequency, and supplies the results to the data adjusting buffer. The data adjusting buffer adjusts the duty of the receive data according to the received comparison results.

摘要翻译： 本发明的数据宽度校正器即使在输入时交叉点已经偏离的数据也适当地调整数据宽度。 数据调整缓冲器将从外部接收到的差分信号改变为单相接收数据，并输出接收数据。 电荷泵将接收数据和锁存的锁存数据之间的HIGH周期的平均时间与具有相同频率的锁存时钟进行比较，并将结果提供给数据调整缓冲器。 数据调整缓冲器根据接收到的比较结果调整接收数据的占空比。

公开(公告)号：US06686779B2

公开(公告)日：2004-02-03

申请号：US10227758

申请日：2002-08-27

申请人： Takefumi Yoshikawa

发明人： Takefumi Yoshikawa

IPC分类号： H03K300

CPC分类号： H04L25/028 ,  H03K19/00323 ,  H04L25/0272 ,  H04L25/0282

摘要： The driver circuit includes a constant current section, a first pad, a second pad, a first switching element, a second switching element, a first resistor, a second resistor, and a control section. The constant current section outputs a prescribed positive or negative current. The first switching element is connected between an output node of the constant current section and the first pad and turned ON/OFF in response to a first signal. The second switching element is connected between the output node of the constant current section and the second pad and turned ON/OFF in response to a second signal. The second signal is complementary to the first signal. The first resistor is connected between a first node receiving a first voltage and the first pad. The second resistor is connected between the first node and the second node. The control section controls a potential at the output node of the constant current section to a prescribed potential.

摘要翻译： 驱动电路包括恒流部分，第一焊盘，第二焊盘，第一开关元件，第二开关元件，第一电阻器，第二电阻器和控制部件。 恒定电流部分输出规定的正或负电流。 第一开关元件连接在恒定电流部分的输出节点和第一焊盘之间，并响应于第一信号而导通/截止。 第二开关元件连接在恒定电流部分的输出节点和第二焊盘之间，并响应于第二信号而导通/截止。 第二信号与第一信号互补。 第一电阻器连接在接收第一电压的第一节点和第一电池块之间。 第二电阻器连接在第一节点和第二节点之间。 控制部将恒定电流部的输出节点的电位控制为规定电位。

公开(公告)号：US06542552B1

公开(公告)日：2003-04-01

申请号：US09468830

申请日：1999-12-22

申请人： Takefumi Yoshikawa ,  Yutaka Terada

发明人： Takefumi Yoshikawa ,  Yutaka Terada

IPC分类号： H03B300

CPC分类号： G06F1/10 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0091 ,  H04L7/04

摘要： A data transmitter according to the present invention includes driver, transmission line and receiver. The receiver includes a transition pulse generator for generating a transition pulse simultaneously with the transition of a data signal output from the driver. If an edge of an internal clock signal overlaps with the transition pulse being applied, then the receiver does not latch the data signal in synchronism with the edge of the internal clock signal. Instead, the receiver obtains and retains a data value opposite to the previous cycle one. On the other hand, while no transition pulses are being applied, the receiver latches the data signal normally responsive to the internal clock signal. Accordingly, the receiver can always accurately retain the very data transmitted through the transmission line, thus improving the reliability of the data received and realizing high-speed data transmission even if the internal clock signal has lagged with respect to the data signal.

摘要翻译： 根据本发明的数据发送器包括驱动器，传输线和接收器。 接收机包括转换脉冲发生器，用于与从驾驶员输出的数据信号的转变同时产生转换脉冲。 如果内部时钟信号的边沿与施加的转换脉冲重叠，则接收器不会与内部时钟信号的边沿同步地锁存数据信号。 相反，接收器获得并保留与前一个周期相反的数据值。 另一方面，当没有施加转换脉冲时，接收器通常响应于内部时钟信号来锁存数据信号。 因此，即使内部时钟信号相对于数据信号滞后，接收机总是可以准确地保持通过传输线传输的非常数据，从而提高接收的数据的可靠性并实现高速数据传输。

公开(公告)号：US06199150B1

公开(公告)日：2001-03-06

申请号：US09114429

申请日：1998-07-13

申请人： Takefumi Yoshikawa

发明人： Takefumi Yoshikawa

IPC分类号： G06F1206

CPC分类号： G06F12/08

摘要： A data memory apparatus includes at least one memory device forming a memory map including at least a first memory area and a second memory area; and an access control unit for controlling access to the at least one memory device so that an access speed to the first memory area is different from an access speed to the second memory area.

摘要翻译： 数据存储装置包括形成至少包括第一存储区和第二存储区的存储器映射的至少一个存储器装置; 以及访问控制单元，用于控制对至少一个存储设备的访问，使得到第一存储区域的访问速度不同于到第二存储区域的访问速度。