公开(公告)号：US09299830B1

公开(公告)日：2016-03-29

申请号：US14706927

申请日：2015-05-07

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Seetharaman Sridhar ,  Christopher Boguslaw Kocon ,  Simon John Molloy ,  Hong Yang

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L21/28114 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66734

Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

Abstract translation: 半导体器件包含垂直MOS晶体管，其沟槽中的沟槽栅极延伸穿过垂直漂移区到漏极区。 这些沟槽在门下有现场板; 场板与漂移区相邻并且具有多个段。 将场板与漂移区分离的沟槽中的电介质衬垫的厚度大于门和主体之间的栅极电介质层。 电介质衬垫在沟槽底部的场板的下段上比在栅极正下方的上段更厚。 沟槽栅极可以与场板电隔离，或者可以连接到上部段。 场板的段可以彼此电隔离或者可以在沟槽中彼此连接。

公开(公告)号：US20240361699A1

公开(公告)日：2024-10-31

申请号：US18308901

申请日：2023-04-28

Applicant: Texas Instruments Incorporated

Inventor： Yunlong Liu ,  Hong Yang ,  Peng Li ,  Yung Shan Chang ,  Sheng Pin Yang ,  Ya Ping Chen

IPC: G03F7/22 ,  G01B5/06 ,  G01B11/06

CPC classification number: G03F7/22 ,  G01B5/06 ,  G01B11/06 ,  G03F7/039

Abstract: A method of forming a microelectronic device includes forming positive tone photoresist on the microelectronic device, filling a trench, extending over a top surface adjacent to the trench, and covering a thickness monitor on a substrate containing the microelectronic device. The photoresist in and over the trench is exposed at a trench energy dose, and the photoresist in the monitor area is exposed at a monitor energy dose that is less than the trench energy dose. The photoresist is developed, leaving photoresist in the trench having an in-trench thickness less than the depth of the trench and leaving an in-monitor thickness of the photoresist on the monitor area less than an unexposed thickness. The in-monitor thickness of the photoresist on the monitor area may be measured and the measured thickness value may be used with a calibration chart to estimate the in-trench thickness of the photoresist.

公开(公告)号：US11037816B2

公开(公告)日：2021-06-15

申请号：US15649774

申请日：2017-07-14

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Michael F Chisholm ,  Yufei Xiong ,  Yunlong Liu

IPC: H01L21/762 ,  C23C16/30

Abstract: In described examples, a device includes a semiconductor substrate; a buried layer; and a trench with inner walls extending from the buried layer to a surface of the semiconductor substrate, the trench having sidewalls, a bottom wall, a barrier layer including a titanium (Ti) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material formed on the barrier layer.

公开(公告)号：US10903345B2

公开(公告)日：2021-01-26

申请号：US15831112

申请日：2017-12-04

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Ho Lin ,  Tianping Lv ,  Sheng Zou ,  Qiuling Jia

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L21/74 ,  H01L23/485 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/40 ,  H01L29/06

Abstract: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

公开(公告)号：US10573553B2

公开(公告)日：2020-02-25

申请号：US16241143

申请日：2019-01-07

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Abbas Ali ,  Yaping Chen ,  Chao Zuo ,  Seetharaman Sridhar ,  Yunlong Liu

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L23/532

Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.

公开(公告)号：US20190296115A1

公开(公告)日：2019-09-26

申请号：US16042834

申请日：2018-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ya ping Chen ,  Hong Yang ,  Peng Li ,  Seetharaman Sridhar ,  Yunlong Liu ,  Rui Liu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.

公开(公告)号：US09865718B1

公开(公告)日：2018-01-09

申请号：US15342896

申请日：2016-11-03

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Ho Lin ,  Tian Ping Lv ,  Sheng Zou ,  Qiu Ling Jia

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/78 ,  H01L21/283 ,  H01L21/3213

CPC classification number: H01L29/7397 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/0653 ,  H01L29/7827

Abstract: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

公开(公告)号：US09653342B2

公开(公告)日：2017-05-16

申请号：US14548029

申请日：2014-11-19

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Hong Yang ,  Christopher Boguslaw Kocon ,  Yufei Xiong ,  Yunlong Liu

IPC: H01L21/762 ,  H01L21/28 ,  H01L21/765 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/765 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/945

Abstract: A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench. A second dielectric layer of a second dielectric material is deposited to at least partially fill the trench. The second dielectric layer is partially etched to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench. The trench is filled with a fill material which provides an electrical conductivity that is at least that of a semiconductor.

公开(公告)号：US08748976B1

公开(公告)日：2014-06-10

申请号：US13787044

申请日：2013-03-06

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  John Manning Savidge Neilson ,  Simon John Molloy ,  Hideaki Kawahara ,  Hong Yang ,  Seetharaman Sridhar ,  Hao Wu ,  Boling Wen

IPC: H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0649 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802

Abstract: A semiconductor device contains a vertical MOS transistor with instances of a vertical RESURF trench on opposite sides of a vertical drift region. The vertical RESURF trench contains a dielectric trench liner on sidewalls, and a lower field plate and an upper field plate above the lower field plate. The dielectric trench liner between the lower field plate and the vertical drift region is thicker than between the upper field plate and the vertical drift region. A gate is disposed over the vertical drift region and is separate from the upper field plate. The upper field plate and the lower field plate are electrically coupled to a source electrode of the vertical MOS transistor.

Abstract translation: 半导体器件包含垂直MOS晶体管，其具有在垂直漂移区域的相对侧上的垂直RESURF沟槽的实例。 垂直RESURF沟槽包含侧壁上的电介质沟槽衬垫，下场板上的下场板和上场板。 下场板和垂直漂移区之间的电介质沟槽衬垫比上场板和垂直漂移区之间厚。 栅极设置在垂直漂移区上方并与上场板分离。 上场板和下场板电耦合到垂直MOS晶体管的源电极。

公开(公告)号：US20240429290A1

公开(公告)日：2024-12-26

申请号：US18751877

申请日：2024-06-24

Applicant: Texas Instruments Incorporated

Inventor： Ya Ping Chen ,  Yunlong Liu ,  Hong Yang ,  Jing Hu ,  Chao Zhuang ,  Peng Li ,  Sheng Pin Yang

IPC: H01L29/40 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes etching a first trench and a second trench in an epitaxial layer over a semiconductor and forming a dielectric liner within the trenches. A photoresist layer is formed within the trenches and over the epitaxial layer and given a post-exposure bake at a first temperature. The photoresist layer is then given an adhesion-promoting bake at a greater second temperature; The photoresist layer is then removed from a top portion the trenches, thereby exposing a top portion of the dielectric liner and leaving a remaining portion of the photoresist in a bottom portion of the trenches. The exposed dielectric liner is etched, thereby leaving a remaining portion of the dielectric liner in the top portion of the trenches. The remaining portion of the photoresist is removed and the trenches are filled with a polysilicon layer.