公开(公告)号：US07799582B2

公开(公告)日：2010-09-21

申请号：US12502523

申请日：2009-07-14

申请人： Kezhakkedath R. Udayakumar ,  Lindsey H. Hall ,  Francis G. Celii ,  Scott R. Summerfelt

发明人： Kezhakkedath R. Udayakumar ,  Lindsey H. Hall ,  Francis G. Celii ,  Scott R. Summerfelt

IPC分类号： H01L21/00

CPC分类号： H01L21/31122 ,  H01L21/0206 ,  H01L21/02071 ,  H01L21/32136 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/65

摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.

摘要翻译： 制造铁电存储器件，同时减轻边缘退化。 在一个或多个半导体层上形成底部电极。 在底部电极上形成铁电层。 顶部电极形成在铁电层上。 上电极，铁电层和底电极被图案化或蚀刻。 进行干洗以减轻边缘退化。 然后进行湿蚀刻/清洁。

公开(公告)号：US07425512B2

公开(公告)日：2008-09-16

申请号：US10721932

申请日：2003-11-25

申请人： Kezhakkedath R. Udayakumar ,  Ted S. Moise ,  Scott R. Summerfelt ,  Martin G. Albrecht ,  William W. Dostalik, Jr. ,  Francis G. Celii

发明人： Kezhakkedath R. Udayakumar ,  Ted S. Moise ,  Scott R. Summerfelt ,  Martin G. Albrecht ,  William W. Dostalik, Jr. ,  Francis G. Celii

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/31616 ,  H01L21/76895 ,  H01L28/55

摘要： The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.

摘要翻译： 本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。 除了其他步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155， 蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，并且蚀刻剂对氧化铝蚀刻停止层130是选择性的。 氧化铝蚀刻停止层也可用作先进CMOS工艺的后端作为通孔蚀刻停止层。

公开(公告)号：US20080081380A1

公开(公告)日：2008-04-03

申请号：US11706722

申请日：2007-02-15

申请人： Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

发明人： Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

IPC分类号： H01L21/00

CPC分类号： H01L28/75 ,  H01L27/11507 ,  H01L28/55

摘要： A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.

摘要翻译： 提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。 该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。 所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用 第二次灰化过程。

公开(公告)号：US08416598B2

公开(公告)日：2013-04-09

申请号：US12781601

申请日：2010-05-17

申请人： Scott R. Summerfelt ,  John Anthony Rodriguez ,  Hugh P. McAdams ,  Steven Craig Bartling

发明人： Scott R. Summerfelt ,  John Anthony Rodriguez ,  Hugh P. McAdams ,  Steven Craig Bartling

IPC分类号： G11C11/22

CPC分类号： G11C29/50 ,  G11C11/22

摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

公开(公告)号：US20120307545A1

公开(公告)日：2012-12-06

申请号：US13150885

申请日：2011-06-01

申请人： Hugh P. McAdams ,  Scott R. Summerfelt ,  Patrick M. Ndai

发明人： Hugh P. McAdams ,  Scott R. Summerfelt ,  Patrick M. Ndai

IPC分类号： G11C11/22

CPC分类号： G11C11/221

摘要： A ferroelectric memory with interleaved pairs of ferroelectric memory cells of the two-transistor, two-capacitor (2T2C) type. Each memory cell in a given pair is constructed as first and second portions, each portion including a transistor and a ferroelectric capacitor. Within each pair, a first portion of a second memory cell is physically located between the first and second portions of the first memory cell. As a result, complementary bit lines for adjacent columns are interleaved with one another. Each sense amplifier is associated with a multiplexer, so that the adjacent columns of the interleaved memory cells are supported by a single sense amplifier. Noise coupling among the bit lines is reduced, and the sense amplifiers can be placed along one side of the array, reducing the number of dummy cells required to eliminate edge cell effects.

摘要翻译： 具有双晶体管，双电容器（2T2C）型的交错成对的铁电存储器单元的铁电存储器。 给定对中的每个存储单元被构造为第一和第二部分，每个部分包括晶体管和铁电电容器。 在每对内，第二存储单元的第一部分物理地位于第一存储单元的第一和第二部分之间。 结果，用于相邻列的互补位线彼此交错。 每个读出放大器与复用器相关联，使得交错存储器单元的相邻列由单个读出放大器支持。 位线之间的噪声耦合减少，并且读出放大器可以沿着阵列的一侧放置，减少了消除边缘单元效应所需的虚拟单元的数量。

公开(公告)号：US08324742B2

公开(公告)日：2012-12-04

申请号：US12185003

申请日：2008-08-01

申请人： Scott R. Summerfelt ,  Stephen A. Meisner ,  John B. Robbins

发明人： Scott R. Summerfelt ,  Stephen A. Meisner ,  John B. Robbins

IPC分类号： H01L23/544 ,  H01L21/76

CPC分类号： H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

摘要： An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.

摘要翻译： 公开了在不透明层下使用的接触金属层中的IC对准标记和用于形成对准标记的工艺。 对准标记包括几微米宽的接触金属场，在接触蚀刻期间形成的PMD柱阵列，接触金属沉积和选择性接触金属去除过程。 柱子被排列成使得接触金属的所有暴露表面是平面的。 一个配置是矩形阵列，其中每隔一行被横向偏移列间距的一半。 选择柱的水平尺寸以使接触金属填充因子最大化，同时在处理期间向下面的基底提供足够的粘附。 作为接触金属去除过程的结果，接触金属比围绕对准标记的PMD层低至少15纳米。

公开(公告)号：US20110079884A1

公开(公告)日：2011-04-07

申请号：US12890137

申请日：2010-09-24

申请人： Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

发明人： Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

IPC分类号： H01L29/06 ,  H01L21/768 ,  H01L21/31

CPC分类号： H01L21/3003 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/6659 ,  H01L29/7833

摘要： An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

摘要翻译： 具有钝化捕获层的集成电路。 具有位于钝化捕获层下面的氢或氘释放层的集成电路。 用于形成具有氢或氘释放层的集成电路的方法。 用于形成具有钝化捕获层的集成电路的方法。

公开(公告)号：US20110014360A1

公开(公告)日：2011-01-20

申请号：US12889851

申请日：2010-09-24

申请人： Stephen Arion Meisner ,  Scott R. Summerfelt

发明人： Stephen Arion Meisner ,  Scott R. Summerfelt

IPC分类号： H05K3/00

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10T29/42 ,  H01L2924/00

摘要： An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.

摘要翻译： 公开了用于光刻图案对准的改进的对准结构。 在低反射率层下的IC中的地形对准标记可能难以注册。 在低反射层的顶部形成反射层，使得对准标记的形貌在反射层中复制，使得能够使用普通的光刻扫描器和步进器对准对准标记。 反射层可以是一个或多个层，并且可以是金属的，电介质的或两者的。 反射层可以在整个IC上是全局的，或者可以是对准标记区域的局部。 可以在随后的处理期间去除反射层，可能来自添加的蚀刻停止层的辅助，或者可以保留在完整的IC中。 所公开的对准标记结构可应用于具有堆叠铁电电容器材料的IC。

公开(公告)号：US07228865B2

公开(公告)日：2007-06-12

申请号：US10447581

申请日：2003-05-28

申请人： Lindsey H. Hall ,  Scott R. Summerfelt

发明人： Lindsey H. Hall ,  Scott R. Summerfelt

IPC分类号： B08B6/00

CPC分类号： G03F7/427 ,  G03F7/42 ,  G03F7/423 ,  G03F7/428 ,  H01L21/02054 ,  H01L21/31122 ,  H01L21/32136 ,  H01L28/55 ,  Y10S134/902

摘要： An embodiment of the invention is a method of cleaning a material stack 2 that has a hard mask top layer 8. The method involves cleaning the material stack 2 with a fluorine-based plasma etch. The method further involves rinsing the material stack 2 with a wet clean process.

摘要翻译： 本发明的一个实施例是清洁具有硬掩模顶层8的材料堆叠2的方法。 该方法包括用基于氟的等离子体蚀刻来清洁材料堆叠2。 该方法还包括用湿清洁工艺漂洗材料堆叠2。

公开(公告)号：US06656748B2

公开(公告)日：2003-12-02

申请号：US10125662

申请日：2002-04-18

申请人： Lindsey H. Hall ,  Scott R. Summerfelt

发明人： Lindsey H. Hall ,  Scott R. Summerfelt

IPC分类号： H01L2100

CPC分类号： H01L21/31122 ,  H01L21/31691 ,  H01L21/32136 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.

摘要翻译： 本发明涉及形成FeRAM集成电路的方法，其包括执行电容器堆叠蚀刻以限定FeRAM电容器。 该方法包括用提供相对于硬掩模的实质选择性的高温BCl3蚀刻来蚀刻PZT铁电层。 或者，PZT铁电层是使用诸如CHF 3的低温氟成分蚀刻化学品进行蚀刻以提供非垂直PZT侧壁轮廓。 这种轮廓防止与随后的底部电极层蚀刻相关联的导电材料沉积在PZT侧壁上，从而防止所得FeRAM电容器的泄漏或“短路”。