公开(公告)号：US4935380A

公开(公告)日：1990-06-19

申请号：US227892

申请日：1988-08-03

申请人： Yoshinori Okumura

发明人： Yoshinori Okumura

IPC分类号： H01L21/266 ,  H01L21/3105 ,  H01L21/336 ,  H01L29/49

CPC分类号： H01L29/66477 ,  H01L21/266 ,  H01L21/3105 ,  H01L29/4933 ,  Y10S257/90

摘要： A polyside gate of a prescribed shape with a protection film formed on the upper surface thereof is formed on a main surface of a semiconductor substrate. The protection film protects the upper surface of the polyside gate from oxidation in heat treatment. Impurities are implanted in the semiconductor substrate using the polyside gate and the protection film as a mask. The implanted impurities are diffused in the semiconductor substrate by the heat treatment, thereby providing a MOS transistor. A polyside gate of a prescribed shape is formed on a main surface of a semiconductor substrate and an interlayer insulating film is formed to cover the polyside gate. A protection film is formed on the interlayer insulating film and a reflow film is further formed thereon. The protection film protects the polyside gate from oxidation. The surface of the reflow film is made smooth by the heat treatment.

摘要翻译： 在半导体衬底的主表面上形成具有形成在其上表面上的保护膜的规定形状的多边形栅极。 保护膜保护多边形闸门的上表面不受热处理的氧化。 使用聚侧栅极和保护膜作为掩模将杂质注入到半导体衬底中。 注入的杂质通过热处理扩散到半导体衬底中，从而提供MOS晶体管。 在半导体衬底的主表面上形成规定形状的多边形栅极，并且形成层间绝缘膜以覆盖多边形栅极。 在层间绝缘膜上形成保护膜，并且还在其上形成回流膜。 保护膜可防止多面体栅极氧化。 通过热处理使回流膜的表面光滑。

公开(公告)号：US06734486B2

公开(公告)日：2004-05-11

申请号：US09222429

申请日：1998-12-29

申请人： Yoshinori Okumura

发明人： Yoshinori Okumura

IPC分类号： H01L27108

CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10888

摘要： An object is to prevent protrusion of a plug from an interlayer insulating film to prevent formation of a step between circuit parts exceeding a step height allowed in a planarization process and also to prevent formation of particles due to a protruded plug. An interlayer insulating film (11) is etched back over the entire surface under an etching condition in which the etching selectivity of a polysilicon plug (13) with respect to the interlayer insulating film (11) is 10, for example, to recess the polysilicon plug (13) to a given depth in a bit line contact hole (12) to form a recessed polysilicon plug (27).

摘要翻译： 目的是防止插塞从层间绝缘膜突出，以防止在平坦化工艺中允许的超过台阶高度的电路部件之间形成台阶，并且还防止由于突出的插头而形成颗粒。 在多晶硅插塞（13）相对于层间绝缘膜（11）的蚀刻选择性为10的蚀刻条件下，在整个表面上蚀刻层间绝缘膜（11），例如使多晶硅 插塞（13）到位线接触孔（12）中的给定深度以形成凹入的多晶硅插塞（27）。

公开(公告)号：US6144079A

公开(公告)日：2000-11-07

申请号：US725386

申请日：1996-10-03

申请人： Masayoshi Shirahata ,  Yoshinori Okumura

发明人： Masayoshi Shirahata ,  Yoshinori Okumura

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/74 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L31/119 ,  H01L27/119 ,  H01L29/76 ,  H01L27/108

CPC分类号： H01L29/105 ,  H01L21/26513 ,  H01L21/74 ,  H01L27/088

摘要： In a semiconductor device, a plurality of MIS transistors of the same conductivity type having different thresholds are formed at a main surface of semiconductor substrate, and impurity profiles on section extending in a depth direction from the main surface of the semiconductor substrate through respective channel regions of the plurality of MIS transistors have peaks located at different depths. This structure is formed by ion implantation performed on the respective channel regions with different implanting energies or different ion species. According to this semiconductor device, the thresholds of the MIS transistors can be individually controlled, and transistor characteristics optimum for uses can be obtained.

公开(公告)号：US5428239A

公开(公告)日：1995-06-27

申请号：US71023

申请日：1993-06-03

申请人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

发明人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

IPC分类号： H01L27/10 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/823892 ,  H01L21/76221 ,  H01L21/823493 ,  H01L27/10805 ,  H01L27/0928 ,  H01L27/105

摘要： A DRAM is formed on a silicon substrate having a retrograde well and a diffusion-type well. The retrograde well has an impurity concentration profile which is set in steps by a plurality of ion-implantations. The diffusion-type well has an impurity concentration profile which changes monotonously by a thermal diffusion. A memory cell array is formed in the retrograde well region. A peripheral circuit is formed in the diffusion-type well region. The retrograde well enhances integration of devices included in the memory cell array. The diffusion-type well enhances the characteristic of insulating isolation between devices.

摘要翻译： 在具有逆行阱和扩散型阱的硅衬底上形成DRAM。 逆行井具有通过多个离子注入步骤设置的杂质浓度分布。 扩散型阱具有通过热扩散单调变化的杂质浓度分布。 在逆行井区域中形成记忆单元阵列。 在扩散型阱区域中形成外围电路。 逆行井增强了存储单元阵列中包含的器件的集成。 扩散型井增强了器件之间绝缘隔离的特性。

公开(公告)号：US5404042A

公开(公告)日：1995-04-04

申请号：US71925

申请日：1993-06-04

申请人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

发明人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L49/00 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L27/10805 ,  H01L27/0218 ,  H01L27/105

摘要： A semiconductor memory device in accordance with the present invention includes a plurality of n well regions and p well regions in a p type silicon substrate. One of the p well regions is connected to an external power supply. Peripheries of the p well region having a memory cell array formed therein are surrounded by an n well region having a potential held at a positive potential. The n well region held at the positive potential prevents electrons introduced into the substrate due to undershoot from entering into a p well region through the p well region connected to the external power supply.

摘要翻译： 根据本发明的半导体存储器件包括p型硅衬底中的多个n阱区和p阱区。 p个阱区中的一个连接到外部电源。 具有其中形成有存储单元阵列的p阱区的周边被具有保持在正电位的电位的n阱区围绕。 保持在正电位的n阱区防止由于下冲通过连接到外部电源的p阱区进入p阱区而引入到衬底中的电子。

公开(公告)号：US5212542A

公开(公告)日：1993-05-18

申请号：US675247

申请日：1991-03-26

申请人： Yoshinori Okumura

发明人： Yoshinori Okumura

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0928

摘要： A complementary field effect transistor with an N channel MOSFET and a P channel MOSFET formed on the same substrate is disclosed. On the P type main surface of the semiconductor substrate, an N channel MOSFET is formed comprising a gate electrode and a pair of impurity regions which becomes a pair of source/drain regions. Each impurity region of the N channel MOSFET comprises an impurity region of relatively low concentration formed so as to extend to beneath the above mentioned gate electrode, and an impurity region having a concentration higher than that of said impurity region having low concentration formed in a position at a distance from said gate electrode joining the impurity region of low concentration. The length of the portion located beneath the above mentioned gate electrode in the surface portion of the impurity region of low concentration is not less than 0.1 .mu.m in the direction identical to the direction of the channel length. This complementary field effect transistor has both reliability and high speed in the N channel MOSFET, and without punch-through in the P channel MOSFET, even though the devices become more minute.

摘要翻译： 公开了一种具有形成在同一衬底上的N沟道MOSFET和P沟道MOSFET的互补场效应晶体管。 在半导体衬底的P型主表面上，形成包括栅电极和成为一对源极/漏极区的一对杂质区的N沟道MOSFET。 N沟道MOSFET的每个杂质区域包括形成为相对低浓度的杂质区域，以延伸到上述栅电极的下方，并且具有比所述低浓度的所述杂质区域的浓度高的杂质区域形成在位置 距离与低浓度的杂质区域接合的所述栅极距离。 在低浓度杂质区域的表面部分中位于上述栅电极下方的部分的长度在与沟道长度方向相同的方向上不小于0.1μm。 这种互补的场效应晶体管在N沟道MOSFET中具有可靠性和高速度，并且即使器件变得更加微小，P沟道MOSFET中也没有穿通。

公开(公告)号：US5173752A

公开(公告)日：1992-12-22

申请号：US690824

申请日：1991-04-26

申请人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

发明人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L27/10873 ,  H01L23/485 ,  H01L27/10817 ,  H01L2924/0002 ,  Y10S257/90

摘要： A semiconductor device incloudes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

摘要翻译： 半导体器件包括MOS型场效应晶体管，其栅电极（4）的表面被第一绝缘膜（5）覆盖，左侧和右侧设置有一对第二绝缘膜（10）。 第一导电层（12,13）形成在源/漏区（8,11）的表面上，并且一对第二绝缘膜（10）中的一个位于栅电极的一侧的表面 （4）。 至少在没有形成第一导电层（12,13）的第二绝缘膜（10）的表面上形成第三绝缘膜（24b）。 在第三绝缘膜（24b）的表面和形成有第三绝缘膜（24b）的源/漏区（8,11）上设置第二导电层（18）。 该结构能够提供可以独立于图案化抗蚀剂掩模的步骤中的误差的影响的自对准中形成接触孔的半导体器件。

公开(公告)号：US4985368A

公开(公告)日：1991-01-15

申请号：US429528

申请日：1989-10-31

申请人： Tatsuya Ishii ,  Yoshinori Okumura ,  Masao Nagatomo

发明人： Tatsuya Ishii ,  Yoshinori Okumura ,  Masao Nagatomo

IPC分类号： H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L29/66181 ,  Y10S257/911

摘要： The semiconductor device in which no stress occurs at the corner portion of the trench comprises a p type semiconductor substrate having a trench and a main surface, a thick insulating film formed on the bottom portion of the trench, a thin insulating film formed on the sidewall portion of the trench and connected to the end portion of the thick insulating film, and an n type impurity region formed in the semiconductor substrate only on the side portion of the thin insulating film.

公开(公告)号：US4912535A

公开(公告)日：1990-03-27

申请号：US232641

申请日：1988-08-08

申请人： Yoshinori Okumura

发明人： Yoshinori Okumura

IPC分类号： H01L27/108

CPC分类号： H01L27/10829

摘要： A semiconductor substrate is formed on its major surface with a first trench and a second trench which is deeper than the first trench. A region held between the first and second trenches serves as a transistor, and impurity regions for serving as source/drain regions are formed on the first and second trench sides. A bit line fills up the first trench and a capacitor electrode fills up the second trench, to be in contact with the impurity regions respectively. A word line is formed on a channel region between the source and drain regions through an oxide film. A semiconductor layer is formed on the major surface of a semiconductor substrate through an oxide film, to be provided with a first trench having the oxide film as a bottom surface and a second trench reaching the semiconductor substrate. The semiconductor layer held between the first and second trenches serves as a transistor, while a bit line and a capacitor electrode fill up the first and second trenches respectively. Two trenches are formed on the major surface of a semiconductor substrate to be provided with a semiconductor device, so that the trenches are filled up with interconnection members. The trenches are respectively provided on their side walls with impurity regions, which are connected with each other by an impurity region formed on the major surface of the semiconductor substrate.

摘要翻译： 半导体衬底在其主表面上形成有比第一沟槽更深的第一沟槽和第二沟槽。 保持在第一沟槽和第二沟槽之间的区域用作晶体管，并且在第一和第二沟槽侧上形成用作源极/漏极区域的杂质区域。 位线填满第一沟槽，电容器电极填充第二沟槽，分别与杂质区域接触。 在源极和漏极区域之间的沟道区域上通过氧化物膜形成字线。 通过氧化膜在半导体衬底的主表面上形成半导体层，以提供具有氧化膜作为底面的第一沟槽和到达半导体衬底的第二沟槽。 保持在第一和第二沟槽之间的半导体层用作晶体管，而位线和电容器电极分别填充第一和第二沟槽。 在半导体衬底的主表面上形成两个沟槽以设置半导体器件，使得沟槽被互连构件填充。 沟槽分别在其侧壁上设置有杂质区域，它们通过形成在半导体衬底的主表面上的杂质区彼此连接。

公开(公告)号：US4894695A

公开(公告)日：1990-01-16

申请号：US169062

申请日：1988-03-17

申请人： Tatsuya Ishii ,  Yoshinori Okumura ,  Masao Nagatomo

发明人： Tatsuya Ishii ,  Yoshinori Okumura ,  Masao Nagatomo

IPC分类号： H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L29/66181 ,  Y10S257/911

摘要： The semiconductor device in which no stress occurs at the corner portion of the trench comprises a p type semiconductor substrate having a trench and a main surface, a thick insulating film formed on the bottom portion of the trench, a thin insulating film formed on the sidewall portion of the trench and connected to the end portion of the thick insulating film, and an n type impurity region formed in the semiconductor substrate only on the side portion of the thin insulating film.

摘要翻译： 在沟槽的角部没有发生应力的半导体器件包括具有沟槽和主表面的ap型半导体衬底，形成在沟槽底部的厚绝缘膜，形成在侧壁部分上的薄绝缘膜 并且连接到厚绝缘膜的端部，并且仅在薄绝缘膜的侧部形成在半导体衬底中的n型杂质区。